From 33d9c4ad7e9e8048e90858edd8e0212e23a0ac8e Mon Sep 17 00:00:00 2001 From: Subrata Banik Date: Tue, 26 May 2020 18:26:54 +0530 Subject: drivers/intel/fsp2_0: Add FSP 2.2 specific support MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit • Based on FSP EAS v2.1 – Backward compatibility is retained. • Add multi-phase silicon initialization to increase the modularity of the FspSiliconInit() API. • Add FspMultiPhaseSiInit() API • FSP_INFO_HEADER changes o Added FspMultiPhaseSiInitEntryOffset • Add FSPS_ARCH_UPD o Added EnableMultiPhaseSiliconInit, bootloaders designed for FSP 2.0/2.1 can disable the FspMultiPhaseSiInit() API and continue to use FspSiliconInit() without change. FSP 2.2 Specification: https://www.intel.com/content/www/us/en/intelligent-systems/intel-firmware-support-package/intel-fsp-overview.html Change-Id: If7177a267f3a9b4cbb60a639f1c737b9a3341913 Signed-off-by: Subrata Banik Reviewed-on: https://review.coreboot.org/c/coreboot/+/41728 Reviewed-by: Srinidhi N Kaushik Tested-by: build bot (Jenkins) --- src/include/console/post_codes.h | 14 ++++++++++++++ 1 file changed, 14 insertions(+) (limited to 'src/include') diff --git a/src/include/console/post_codes.h b/src/include/console/post_codes.h index 00a2ad3dec..0c6655cec8 100644 --- a/src/include/console/post_codes.h +++ b/src/include/console/post_codes.h @@ -288,6 +288,20 @@ */ #define POST_FSP_SILICON_EXIT 0x99 +/** + * \brief Before calling FSP Multiphase SiliconInit + * + * Going to call into FSP binary for Multiple phase SI Init + */ +#define POST_FSP_MULTI_PHASE_SI_INIT_ENTRY 0xa0 + +/** + * \brief After calling FSP Multiphase SiliconInit + * + * FSP binary returned from Multiple phase SI Init + */ +#define POST_FSP_MULTI_PHASE_SI_INIT_EXIT 0xa1 + /** * \brief Entry into elf boot * -- cgit v1.2.3