From 16ab9bdcd578612bb3822373547f939eb90afd82 Mon Sep 17 00:00:00 2001 From: Subrata Banik Date: Fri, 30 Jul 2021 17:01:11 +0530 Subject: soc/intel/common: Calculate and configure SF Mask 2 As per TGL EDS, two ways will be controlled with one bit of SF QoS register hence, this patch introduces SF_MASK_2WAYS_PER_BIT Kconfig to allow SoC users to select SF_MASK_2WAYS_PER_BIT to follow the EDS recommendation. Calculate SF masks 2: 1. if CONFIG_SF_MASK_2WAYS_PER_BIT: a. data_ways = data_ways / 2 Also, program SF Mask#2 using below logic: 2. Set SF_MASK_2 = (1 << data_ways) - 1 Change-Id: I442bed75f13d26f357cfb32c54c5fe9efa4b474b Signed-off-by: Subrata Banik Reviewed-on: https://review.coreboot.org/c/coreboot/+/56717 Tested-by: build bot (Jenkins) Reviewed-by: Tim Wawrzynczak --- src/include/cpu/x86/msr.h | 2 ++ 1 file changed, 2 insertions(+) (limited to 'src/include') diff --git a/src/include/cpu/x86/msr.h b/src/include/cpu/x86/msr.h index 26f1dcb6cf..9e7e6fd8ba 100644 --- a/src/include/cpu/x86/msr.h +++ b/src/include/cpu/x86/msr.h @@ -88,6 +88,8 @@ #define IA32_HWP_CAPABILITIES 0x771 #define IA32_HWP_REQUEST 0x774 #define IA32_HWP_STATUS 0x777 +#define IA32_SF_QOS_INFO 0xc87 +#define IA32_SF_WAY_COUNT_MASK 0x3f #define IA32_PQR_ASSOC 0xc8f /* MSR bits 33:32 encode slot number 0-3 */ #define IA32_PQR_ASSOC_MASK (1 << 0 | 1 << 1) -- cgit v1.2.3