From 107f72e674a3fbe2cadb24d98bba53f432bc2e0c Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Ky=C3=B6sti=20M=C3=A4lkki?= Date: Mon, 6 Jan 2014 11:06:26 +0200 Subject: Re-declare CACHE_ROM_SIZE as aligned ROM_SIZE for MTRR MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit This change allows Kconfig options ROM_SIZE and CBFS_SIZE to be set with values that are not power of 2. The region programmed as WB cacheable will include all of ROM_SIZE. Side-effects to consider: Memory region below flash may be tagged WRPROT cacheable. As an example, with ROM_SIZE of 12 MB, CACHE_ROM_SIZE would be 16 MB. Since this can overlap CAR, we add an explicit test and fail on compile should this happen. To work around this problem, one needs to use CACHE_ROM_SIZE_OVERRIDE in the mainboard Kconfig and define a smaller region for WB cache. With this change flash regions outside CBFS are also tagged WRPROT cacheable. This covers IFD and ME and sections ChromeOS may use. Change-Id: I5e577900ff7e91606bef6d80033caaed721ce4bf Signed-off-by: Kyösti Mälkki Reviewed-on: http://review.coreboot.org/4625 Tested-by: build bot (Jenkins) Reviewed-by: Vladimir Serbinenko --- src/include/cpu/x86/mtrr.h | 34 +++++++++++++++++++++++++++++++--- 1 file changed, 31 insertions(+), 3 deletions(-) (limited to 'src/include') diff --git a/src/include/cpu/x86/mtrr.h b/src/include/cpu/x86/mtrr.h index 913ba47487..bbcde8a658 100644 --- a/src/include/cpu/x86/mtrr.h +++ b/src/include/cpu/x86/mtrr.h @@ -96,6 +96,13 @@ static inline long x86_mtrr_rom_cache_var_index(void) { return -1; } void set_var_mtrr(unsigned reg, unsigned base, unsigned size, unsigned type); #endif +/* Align up to next power of 2, suitable for ROMCC and assembler too. + * Range of result 256kB to 128MB is good enough here. + */ +#define _POW2_MASK(x) ((x>>1)|(x>>2)|(x>>3)|(x>>4)|(x>>5)| \ + (x>>6)|(x>>7)|(x>>8)|((1<<18)-1)) +#define _ALIGN_UP_POW2(x) ((x + _POW2_MASK(x)) & ~_POW2_MASK(x)) + #if !defined(CONFIG_RAMTOP) # error "CONFIG_RAMTOP not defined" #endif @@ -104,11 +111,32 @@ void set_var_mtrr(unsigned reg, unsigned base, unsigned size, unsigned type); # error "CONFIG_XIP_ROM_SIZE is not a power of 2" #endif -#if ((CONFIG_CACHE_ROM_SIZE & (CONFIG_CACHE_ROM_SIZE -1)) != 0) -# error "CONFIG_CACHE_ROM_SIZE is not a power of 2" +/* Select CACHE_ROM_SIZE to use with MTRR setup. For most cases this + * resolves to a suitable CONFIG_ROM_SIZE but some odd cases need to + * use CONFIG_CACHE_ROM_SIZE_OVERRIDE in the mainboard Kconfig. + */ +#if (CONFIG_CACHE_ROM_SIZE_OVERRIDE != 0) +# define CACHE_ROM_SIZE CONFIG_CACHE_ROM_SIZE_OVERRIDE +#else +# if ((CONFIG_ROM_SIZE & (CONFIG_ROM_SIZE-1)) == 0) +# define CACHE_ROM_SIZE CONFIG_ROM_SIZE +# else +# define CACHE_ROM_SIZE _ALIGN_UP_POW2(CONFIG_ROM_SIZE) +# if (CACHE_ROM_SIZE < CONFIG_ROM_SIZE) || (CACHE_ROM_SIZE >= (2 * CONFIG_ROM_SIZE)) +# error "CACHE_ROM_SIZE is not optimal." +# endif +# endif +#endif + +#if ((CACHE_ROM_SIZE & (CACHE_ROM_SIZE-1)) != 0) +# error "CACHE_ROM_SIZE is not a power of 2." #endif -#define CACHE_ROM_BASE (((1<<20) - (CONFIG_CACHE_ROM_SIZE>>12))<<12) +#define CACHE_ROM_BASE (((1<<20) - (CACHE_ROM_SIZE>>12))<<12) + +#if ((CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE) * 1UL > CACHE_ROM_BASE * 1UL) +# error "CAR region (WB) and flash (WP) regions overlap." +#endif #if (CONFIG_RAMTOP & (CONFIG_RAMTOP - 1)) != 0 # error "CONFIG_RAMTOP must be a power of 2" -- cgit v1.2.3