From 0f45e17f564a657ddf9804124e4e30da0edb1d13 Mon Sep 17 00:00:00 2001 From: Elyes Haouas Date: Mon, 6 May 2024 10:08:51 +0200 Subject: dram/ddr5: Use the same naming convention as DDR{2,3,4} Change-Id: I2cc38926b56315d4a828311917ff58051b34b777 Signed-off-by: Elyes Haouas Reviewed-on: https://review.coreboot.org/c/coreboot/+/82214 Tested-by: build bot (Jenkins) Reviewed-by: Angel Pons --- src/include/device/dram/ddr5.h | 28 ++++++++++++++-------------- 1 file changed, 14 insertions(+), 14 deletions(-) (limited to 'src/include') diff --git a/src/include/device/dram/ddr5.h b/src/include/device/dram/ddr5.h index 37182da365..78d18b24f8 100644 --- a/src/include/device/dram/ddr5.h +++ b/src/include/device/dram/ddr5.h @@ -15,20 +15,20 @@ /** Maximum SPD size supported */ #define SPD_SIZE_MAX_DDR5 1024 -enum ddr5_module_type { - DDR5_SPD_RDIMM = 0x01, - DDR5_SPD_UDIMM = 0x02, - DDR5_SPD_SODIMM = 0x03, - DDR5_SPD_LRDIMM = 0x04, - DDR5_SPD_MINI_RDIMM = 0x05, - DDR5_SPD_MINI_UDIMM = 0x06, - DDR5_SPD_72B_SO_UDIMM = 0x08, - DDR5_SPD_72B_SO_RDIMM = 0x09, - DDR5_SPD_SOLDERED_DOWN = 0x0b, - DDR5_SPD_16B_SO_DIMM = 0x0c, - DDR5_SPD_32B_SO_RDIMM = 0x0d, - DDR5_SPD_1DPC = 0x0e, - DDR5_SPD_2DPC = 0x0f, +enum spd_dimm_type_ddr5 { + SPD_DDR5_DIMM_TYPE_RDIMM = 0x01, + SPD_DDR5_DIMM_TYPE_UDIMM = 0x02, + SPD_DDR5_DIMM_TYPE_SODIMM = 0x03, + SPD_DDR5_DIMM_TYPE_LRDIMM = 0x04, + SPD_DDR5_DIMM_TYPE_MINI_RDIMM = 0x05, + SPD_DDR5_DIMM_TYPE_MINI_UDIMM = 0x06, + SPD_DDR5_DIMM_TYPE_72B_SO_UDIMM = 0x08, + SPD_DDR5_DIMM_TYPE_72B_SO_RDIMM = 0x09, + SPD_DDR5_DIMM_TYPE_SOLDERED_DOWN = 0x0b, + SPD_DDR5_DIMM_TYPE_16B_SO_DIMM = 0x0c, + SPD_DDR5_DIMM_TYPE_32B_SO_RDIMM = 0x0d, + SPD_DDR5_DIMM_TYPE_1DPC = 0x0e, + SPD_DDR5_DIMM_TYPE_2DPC = 0x0f, }; /** -- cgit v1.2.3