From 0755ab98a5f0d6632a4fc856d8812f5e70983a13 Mon Sep 17 00:00:00 2001 From: Subrata Banik Date: Wed, 12 Jul 2017 15:31:06 +0530 Subject: intel/fsp: Add and use new post codes for FSP phase indication New post codes are POST_FSP_MEMORY_EXIT POST_FSP_SILICON_EXIT This patch will make it more consistent to debug FSP hang and reset issues. Bug=none Branch=none TEST=Build and Boot on eve Change-Id: I93004a09c2a3a97ac9458a0f686ab42415af19fb Signed-off-by: Subrata Banik Reviewed-on: https://review.coreboot.org/20541 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin Reviewed-by: Furquan Shaikh --- src/include/console/post_codes.h | 14 ++++++++++++++ 1 file changed, 14 insertions(+) (limited to 'src/include') diff --git a/src/include/console/post_codes.h b/src/include/console/post_codes.h index 1368aa865c..0277337a0a 100644 --- a/src/include/console/post_codes.h +++ b/src/include/console/post_codes.h @@ -272,6 +272,20 @@ */ #define POST_OS_ENTER_WAKE 0x97 +/** + * \brief After calling FSP MemoryInit + * + * FSP binary returned from MemoryInit phase + */ +#define POST_FSP_MEMORY_EXIT 0x98 + +/** + * \brief After calling FSP SiliconInit + * + * FSP binary returned from SiliconInit phase + */ +#define POST_FSP_SILICON_EXIT 0x99 + /** * \brief Entry into elf boot * -- cgit v1.2.3