From 070a10f7593014f1ae8a0f15d34293f59790f9cf Mon Sep 17 00:00:00 2001 From: "Ronald G. Minnich" Date: Thu, 4 May 2006 23:05:49 +0000 Subject: mods for early printing on OLPC git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2297 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1 --- src/include/cpu/amd/gx2def.h | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) (limited to 'src/include') diff --git a/src/include/cpu/amd/gx2def.h b/src/include/cpu/amd/gx2def.h index 0c636ef2b5..074e36110b 100644 --- a/src/include/cpu/amd/gx2def.h +++ b/src/include/cpu/amd/gx2def.h @@ -89,7 +89,8 @@ #define MSR_VIP ((GL1_VIP << 26) + MSR_GLIU1) #define MSR_AES ((GL1_AES << 26) + MSR_GLIU1) /* South Bridge*/ -#define MSR_SB (SB_PORT << 23) + MSR_PCI /* address to the SouthBridge*/ +#define SB_PORT 2 /* port of the SouthBridge */ +#define MSR_SB ((SB_PORT << 23) + MSR_PCI) /* address to the SouthBridge*/ #define SB_SHIFT 20 /* 29 -> 26 -> 23 -> 20...... When making a SB address uses this shift.*/ @@ -502,7 +503,7 @@ #define CS5535_IDSEL 0x02000000 // IDSEL = AD25, device #15 #define CHIPSET_DEV_NUM 15 #define IDSEL_BASE 11 // bit 11 = device 1 -#define SB_PORT 2 // port of the SouthBridge + /* standard AMD post definitions -- might as well use them. */ #define POST_Output_Port (0x080) /* port to write post codes to*/ -- cgit v1.2.3