From 323e5a84eb53c35ed9b58fb7e5045cc8b7c42986 Mon Sep 17 00:00:00 2001
From: Tim Chu <Tim.Chu@quantatw.com>
Date: Thu, 27 Oct 2022 03:03:59 +0000
Subject: src/include/smbios: Add definition for smbios type 4 and type 9

Add definition for smbios type 4 and type 9

Signed-off-by: Tim Chu <Tim.Chu@quantatw.com>
Change-Id: I559995b0204f8e5bdeef2c0f8b394f9011d72240
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68902
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jonathan Zhang <jonzhang@fb.com>
Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
---
 src/include/smbios.h | 11 +++++++++++
 1 file changed, 11 insertions(+)

(limited to 'src/include/smbios.h')

diff --git a/src/include/smbios.h b/src/include/smbios.h
index 3611eb6c2e..cb317b03a3 100644
--- a/src/include/smbios.h
+++ b/src/include/smbios.h
@@ -485,6 +485,16 @@ struct smbios_type4 {
 #define SMBIOS_PROCESSOR_STATUS_POPULATED		(1 << 6)
 #define SMBIOS_PROCESSOR_STATUS_CPU_ENABLED		(1 << 0)
 
+/* defines for processor family */
+#define SMBIOS_PROCESSOR_FAMILY_OTHER			0x01
+#define SMBIOS_PROCESSOR_FAMILY_UNKNOWN			0x02
+#define SMBIOS_PROCESSOR_FAMILY_XEON			0xb3
+
+/* defines for processor characteristics */
+#define PROCESSOR_64BIT_CAPABLE				(1 << 2)
+#define PROCESSOR_MULTI_CORE				(1 << 3)
+#define PROCESSOR_POWER_PERFORMANCE_CONTROL		(1 << 7)
+
 /* defines for supported_sram_type/current_sram_type */
 
 #define SMBIOS_CACHE_SRAM_TYPE_OTHER			(1 << 0)
@@ -721,6 +731,7 @@ enum misc_slot_type {
 	SlotTypePciExpressMini52pinWithBSKO = 0x21,
 	SlotTypePciExpressMini52pinWithoutBSKO = 0x22,
 	SlotTypePciExpressMini76pin = 0x23,
+	SlotTypePciExpressOCPNIC30SFF = 0x26,
 	SlotTypePC98C20 = 0xA0,
 	SlotTypePC98C24 = 0xA1,
 	SlotTypePC98E = 0xA2,
-- 
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