From bd74a4b2d25268f7035a4478da31f27baac2aecc Mon Sep 17 00:00:00 2001 From: Aaron Durbin Date: Fri, 6 Mar 2015 23:17:33 -0600 Subject: coreboot: common stage cache Many chipsets were using a stage cache for reference code or when using a relocatable ramstage. Provide a common API for the chipsets to use while reducing code duplication. Change-Id: Ia36efa169fe6bd8a3dbe07bf57a9729c7edbdd46 Signed-off-by: Aaron Durbin Reviewed-on: http://review.coreboot.org/8625 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones --- src/include/romstage_handoff.h | 4 ---- 1 file changed, 4 deletions(-) (limited to 'src/include/romstage_handoff.h') diff --git a/src/include/romstage_handoff.h b/src/include/romstage_handoff.h index 376b4fd119..09934ca442 100644 --- a/src/include/romstage_handoff.h +++ b/src/include/romstage_handoff.h @@ -36,10 +36,6 @@ struct romstage_handoff { uint8_t s3_resume; uint8_t reboot_required; uint8_t reserved[2]; - /* The ramstage_entry_point is cached in the stag loading path. This - * cached value can only be utilized when the chipset code properly - * fills in the s3_resume field above. */ - uint32_t ramstage_entry_point; }; #if defined(__ROMSTAGE__) -- cgit v1.2.3