From bc36e298f998f8126837b4ea8e2e56566dc078dc Mon Sep 17 00:00:00 2001 From: Michael Niewöhner Date: Wed, 2 Oct 2019 20:07:16 +0200 Subject: soc/intel/skylake: search for PME wake event on all root ports MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Currently only the PCIe ports 1-12 are checked for a wake event. Add ELOG wake sources for ports 13-24, if they exist. Change-Id: Ic96e5101ad57bdecd8cbdb66379bc274ae790e01 Signed-off-by: Michael Niewöhner Reviewed-on: https://review.coreboot.org/c/coreboot/+/35764 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin Reviewed-by: Furquan Shaikh --- src/include/elog.h | 12 ++++++++++++ 1 file changed, 12 insertions(+) (limited to 'src/include/elog.h') diff --git a/src/include/elog.h b/src/include/elog.h index 0574819e0d..0328a865a4 100644 --- a/src/include/elog.h +++ b/src/include/elog.h @@ -149,6 +149,18 @@ #define ELOG_WAKE_SOURCE_PME_XHCI_USB_2 0x1d #define ELOG_WAKE_SOURCE_PME_XHCI_USB_3 0x1e #define ELOG_WAKE_SOURCE_PME_WIFI 0x1f +#define ELOG_WAKE_SOURCE_PME_PCIE13 0x20 +#define ELOG_WAKE_SOURCE_PME_PCIE14 0x21 +#define ELOG_WAKE_SOURCE_PME_PCIE15 0x22 +#define ELOG_WAKE_SOURCE_PME_PCIE16 0x23 +#define ELOG_WAKE_SOURCE_PME_PCIE17 0x24 +#define ELOG_WAKE_SOURCE_PME_PCIE18 0x25 +#define ELOG_WAKE_SOURCE_PME_PCIE19 0x26 +#define ELOG_WAKE_SOURCE_PME_PCIE20 0x27 +#define ELOG_WAKE_SOURCE_PME_PCIE21 0x28 +#define ELOG_WAKE_SOURCE_PME_PCIE22 0x29 +#define ELOG_WAKE_SOURCE_PME_PCIE23 0x2a +#define ELOG_WAKE_SOURCE_PME_PCIE24 0x2b struct elog_event_data_wake { u8 source; -- cgit v1.2.3