From a0bc90e4abfe2ed87865d365436ed99311954e27 Mon Sep 17 00:00:00 2001 From: Maximilian Brune Date: Mon, 8 Aug 2022 12:30:47 +0200 Subject: Add missing ADL-S device identification R680E, Q670E, H610E are the ADL-S IoT variants TEST=Boot ADL-S RVP DDR5 and see silicon info is reported as PCH: AlderLake-S R680E Signed-off-by: Maximilian Brune Change-Id: I1804994b4b72f0484eabb15323736679d2668078 Reviewed-on: https://review.coreboot.org/c/coreboot/+/66544 Tested-by: build bot (Jenkins) Reviewed-by: Lean Sheng Tan Reviewed-by: Angel Pons --- src/include/device/pci_ids.h | 3 +++ 1 file changed, 3 insertions(+) (limited to 'src/include/device') diff --git a/src/include/device/pci_ids.h b/src/include/device/pci_ids.h index ec48a120ec..a8cbade924 100644 --- a/src/include/device/pci_ids.h +++ b/src/include/device/pci_ids.h @@ -3040,6 +3040,9 @@ #define PCI_DID_INTEL_ADP_S_ESPI_29 0x7a9d #define PCI_DID_INTEL_ADP_S_ESPI_30 0x7a9e #define PCI_DID_INTEL_ADP_S_ESPI_31 0x7a9f +#define PCI_DID_INTEL_ADP_S_ESPI_H610E 0x7a92 +#define PCI_DID_INTEL_ADP_S_ESPI_Q670E 0x7a91 +#define PCI_DID_INTEL_ADP_S_ESPI_R680E 0x7a90 #define PCI_DID_INTEL_ADP_S_H610 0x7a87 #define PCI_DID_INTEL_ADP_S_B660 0x7a86 #define PCI_DID_INTEL_ADP_S_H670 0x7a85 -- cgit v1.2.3