From 4fa5fa5088503ff5c168b4fb8d548dd90034d29e Mon Sep 17 00:00:00 2001 From: Aaron Durbin Date: Fri, 22 Mar 2013 22:16:58 -0500 Subject: resources: introduce IORESOURCE_WRCOMB Certain MMIO resources can be set to a write-combining cacheable mode to increase performance. Typical resources that use this would be graphics memory. Change-Id: Icd96c720f86f7e2f19a6461bb23cb323124eb68e Signed-off-by: Aaron Durbin Reviewed-on: http://review.coreboot.org/2891 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich --- src/include/device/resource.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'src/include/device') diff --git a/src/include/device/resource.h b/src/include/device/resource.h index 6b66605a6a..4bd9698e2c 100644 --- a/src/include/device/resource.h +++ b/src/include/device/resource.h @@ -21,7 +21,7 @@ * to the bus below. */ #define IORESOURCE_BRIDGE 0x00080000 /* The IO resource has a bus below it. */ - +#define IORESOURCE_WRCOMB 0x00100000 /* Write combining resource. */ #define IORESOURCE_RESERVE 0x10000000 /* The resource needs to be reserved in the coreboot table */ #define IORESOURCE_STORED 0x20000000 /* The IO resource assignment has been stored in the device */ #define IORESOURCE_ASSIGNED 0x40000000 /* An IO resource that has been assigned a value */ -- cgit v1.2.3