From 3521e260e3477b3c49835eb2330671e0bc7abe65 Mon Sep 17 00:00:00 2001 From: Kyösti Mälkki Date: Wed, 26 Dec 2018 19:33:28 +0200 Subject: device/pci_early: Fixes for __SIMPLE_DEVICE__ MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The feature is used to enable PCI MMIO accesses behind PCIe links (or bridges) before PCI enumeration has been completed. Add the feature for bootblock, verstage and postcar, it is required with add-on PCIe serial cards for early console output. It's up to the board specific code to configure PCIe root port prior to calling console_init() for this to work. Remove feature from ramstage, it bypasses any resource allocations and bus number assignments. For the moment PCI configuration support before ramstage is available only on ARCH_X86. Also switch from device_t to pci_devfn_t. Change-Id: I08acec68b6f17f4d73d30039cc41274492ea4f45 Signed-off-by: Kyösti Mälkki Reviewed-on: https://review.coreboot.org/c/30496 Tested-by: build bot (Jenkins) Reviewed-by: Arthur Heymans --- src/include/device/pci.h | 2 ++ 1 file changed, 2 insertions(+) (limited to 'src/include/device') diff --git a/src/include/device/pci.h b/src/include/device/pci.h index f1ab91bbc7..7cf7e0695e 100644 --- a/src/include/device/pci.h +++ b/src/include/device/pci.h @@ -145,6 +145,8 @@ unsigned int pci_find_capability(struct device *dev, unsigned int cap); #endif /* __SIMPLE_DEVICE__ */ void pci_early_bridge_init(void); +void pci_early_mmio_window(pci_devfn_t p2p_bridge, u32 mmio_base, + u32 mmio_size); int pci_early_device_probe(u8 bus, u8 dev, u32 mmio_base); #ifndef __ROMCC__ -- cgit v1.2.3