From 305ee06933292d7520292ee0a1910f9062e96298 Mon Sep 17 00:00:00 2001 From: Elyes Haouas Date: Tue, 30 Apr 2024 22:38:25 +0200 Subject: spd.h: Move enum ddr5_module_type to ddr5.h Move specific enum ddr5_module_type to . Change-Id: Ie38d1e99fa46c278e60ced2d3eef29ca823d4b1d Signed-off-by: Elyes Haouas Reviewed-on: https://review.coreboot.org/c/coreboot/+/82123 Tested-by: build bot (Jenkins) Reviewed-by: Jakub Czapiga --- src/include/device/dram/ddr5.h | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) (limited to 'src/include/device') diff --git a/src/include/device/dram/ddr5.h b/src/include/device/dram/ddr5.h index ff1604a808..37182da365 100644 --- a/src/include/device/dram/ddr5.h +++ b/src/include/device/dram/ddr5.h @@ -15,6 +15,22 @@ /** Maximum SPD size supported */ #define SPD_SIZE_MAX_DDR5 1024 +enum ddr5_module_type { + DDR5_SPD_RDIMM = 0x01, + DDR5_SPD_UDIMM = 0x02, + DDR5_SPD_SODIMM = 0x03, + DDR5_SPD_LRDIMM = 0x04, + DDR5_SPD_MINI_RDIMM = 0x05, + DDR5_SPD_MINI_UDIMM = 0x06, + DDR5_SPD_72B_SO_UDIMM = 0x08, + DDR5_SPD_72B_SO_RDIMM = 0x09, + DDR5_SPD_SOLDERED_DOWN = 0x0b, + DDR5_SPD_16B_SO_DIMM = 0x0c, + DDR5_SPD_32B_SO_RDIMM = 0x0d, + DDR5_SPD_1DPC = 0x0e, + DDR5_SPD_2DPC = 0x0f, +}; + /** * Converts DDR5 clock speed in MHz to the standard reported speed in MT/s */ -- cgit v1.2.3