From 3102fd0f8f1d70d5e25997f15374ff5e2b39957c Mon Sep 17 00:00:00 2001
From: Sridhar Siricilla <sridhar.siricilla@intel.com>
Date: Mon, 7 Jun 2021 23:38:17 +0530
Subject: soc/intel: Add Alder Lake's GT device ID

Add Alder Lake specific graphics device ID. The document# 641765 lists
the id 0x46a8.

TEST=Verify boot on brya

Signed-off-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
Change-Id: I6f36256505a3e07c6197079ea2013991e841401b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55256
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
Reviewed-by: Ronak Kanabar <ronak.kanabar@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/include/device/pci_ids.h | 1 +
 1 file changed, 1 insertion(+)

(limited to 'src/include/device/pci_ids.h')

diff --git a/src/include/device/pci_ids.h b/src/include/device/pci_ids.h
index eeb23aeea3..8276a3e1be 100644
--- a/src/include/device/pci_ids.h
+++ b/src/include/device/pci_ids.h
@@ -3816,6 +3816,7 @@
 #define PCI_DEVICE_ID_INTEL_ADL_P_GT2_1			0x46b0
 #define PCI_DEVICE_ID_INTEL_ADL_P_GT2_2			0x46a1
 #define PCI_DEVICE_ID_INTEL_ADL_P_GT2_3			0x46a3
+#define PCI_DEVICE_ID_INTEL_ADL_P_GT2_4			0x46a8
 #define PCI_DEVICE_ID_INTEL_ADL_S_GT1			0x4680
 #define PCI_DEVICE_ID_INTEL_ADL_M_GT1			0x46c0
 
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