From e0dae99b47faf6e750938bc52550128a4351f93e Mon Sep 17 00:00:00 2001 From: Lee Leahy Date: Thu, 15 Jan 2015 15:02:55 -0800 Subject: PCI - Add interrupt disable bit definition BRANCH=none BUG=None TEST=Build Braswell/Strago Change-Id: I11a4c02af3b40edf2252b9e20298941b99f31d21 Signed-off-by: Stefan Reinauer Original-Commit-Id: 1629d7454a3d4adb8930d14849c41c9a711f4c9a Original-Change-Id: Ie907637f7c823de681ef2e315e803dffc6ad33d3 Original-Signed-off-by: Lee Leahy Original-Reviewed-on: https://chromium-review.googlesource.com/241081 Original-Reviewed-by: Duncan Laurie Reviewed-on: http://review.coreboot.org/9487 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi --- src/include/device/pci_def.h | 1 + 1 file changed, 1 insertion(+) (limited to 'src/include/device/pci_def.h') diff --git a/src/include/device/pci_def.h b/src/include/device/pci_def.h index c49e4ebf36..ef3427b4e7 100644 --- a/src/include/device/pci_def.h +++ b/src/include/device/pci_def.h @@ -18,6 +18,7 @@ #define PCI_COMMAND_WAIT 0x80 /* Enable address/data stepping */ #define PCI_COMMAND_SERR 0x100 /* Enable SERR */ #define PCI_COMMAND_FAST_BACK 0x200 /* Enable back-to-back writes */ +#define PCI_COMMAND_INT_DISABLE 0x400 /* Interrupt disable */ #define PCI_STATUS 0x06 /* 16 bits */ #define PCI_STATUS_CAP_LIST 0x10 /* Support Capability List */ -- cgit v1.2.3