From 9514d47d3c7296ff98bb7a590e36ee548b40e369 Mon Sep 17 00:00:00 2001 From: Subrata Banik Date: Wed, 20 Mar 2019 14:56:27 +0530 Subject: device/pci_device: Add generic subsystem programming logic MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit This patch adds generic log to perform subsystem programming based on header type. Type 0: subsystem offset 0x2C Type 2: subsystem offset 0x40 Type 1: Read CAP ID 0xD to know cap offset start, offset 4 to locate subsystem vendor id. Change-Id: Id8aed6dac24517e93cd55d6bb3b254b7b4d950d3 Signed-off-by: Subrata Banik Reviewed-on: https://review.coreboot.org/c/coreboot/+/31983 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki Reviewed-by: David Guckian Reviewed-by: Furquan Shaikh --- src/include/device/pci_def.h | 1 + 1 file changed, 1 insertion(+) (limited to 'src/include/device/pci_def.h') diff --git a/src/include/device/pci_def.h b/src/include/device/pci_def.h index f9ce1a6382..bc5bc79e28 100644 --- a/src/include/device/pci_def.h +++ b/src/include/device/pci_def.h @@ -198,6 +198,7 @@ #define PCI_CAP_ID_HT 0x08 /* Hypertransport */ #define PCI_CAP_ID_EHCI_DEBUG 0x0A /* EHCI debug port */ #define PCI_CAP_ID_SHPC 0x0C /* PCI Standard Hot-Plug Controller */ +#define PCI_CAP_ID_SSVID 0x0D /* Bridge subsystem vendor/device ID */ #define PCI_CAP_ID_PCIE 0x10 /* PCI Express */ #define PCI_CAP_ID_MSIX 0x11 /* MSI-X */ #define PCI_CAP_LIST_NEXT 1 /* Next capability in the list */ -- cgit v1.2.3