From 31c6e632cf607ad8364c49b934f726ef02486d46 Mon Sep 17 00:00:00 2001 From: Kenji Chen Date: Sat, 4 Oct 2014 01:14:44 +0800 Subject: PCIe: Add L1 Sub-State support. Enable L1 Sub-State when both root port and endpoint support it. [pg: keyed the feature to MMCONF_SUPPORT, otherwise boards without that capability fail to build.] Change-Id: Id11fc7c73eb865411747eef63f5f901e00a17f84 Signed-off-by: Patrick Georgi Original-Commit-Id: 6ac04ad7e2261846e40da297f7fa317ccebda092 Original-BUG=chrome-os-partner:31424 Original-TEST=Build a image and run on Samus proto boards to check if the settings are applied correctly. I just only have proto boards and need someone having EVT boards to confirm the settings. Original-Signed-off-by: Kenji Chen Original-Change-Id: Id1b5a52ff0b896f4531c4a6e68e70a2cea8c736a Original-Reviewed-on: https://chromium-review.googlesource.com/221436 Original-Reviewed-by: Duncan Laurie Reviewed-on: http://review.coreboot.org/8832 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer --- src/include/device/pci_def.h | 6 ++++++ 1 file changed, 6 insertions(+) (limited to 'src/include/device/pci_def.h') diff --git a/src/include/device/pci_def.h b/src/include/device/pci_def.h index 403978584d..c49e4ebf36 100644 --- a/src/include/device/pci_def.h +++ b/src/include/device/pci_def.h @@ -405,6 +405,12 @@ #define PCI_EXT_CAP_ID_DSN 3 #define PCI_EXT_CAP_ID_PWR 4 +/* Extended Capability lists*/ +#define PCIE_EXT_CAP_OFFSET 0x100 +#define PCIE_EXT_CAP_AER_ID 0x0001 +#define PCIE_EXT_CAP_L1SS_ID 0x001E +#define PCIE_EXT_CAP_LTR_ID 0x0018 + /* Advanced Error Reporting */ #define PCI_ERR_UNCOR_STATUS 4 /* Uncorrectable Error Status */ #define PCI_ERR_UNC_TRAIN 0x00000001 /* Training */ -- cgit v1.2.3