From 18cb1340f185150b9708257ba8024b6900706083 Mon Sep 17 00:00:00 2001 From: Kane Chen Date: Wed, 1 Oct 2014 11:13:54 +0800 Subject: device/pciexp: Add support for PCIe CLK power management MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Set PCIe "Enable Clock Power Management", if endpoint supports it. BUG=chrome-os-partner:31424 BRANCH=none TEST=build and boot on rambi, check Enable Clock Power Management in link control register is set properly Change-Id: Ie54110d1ef42184cfcf47c9fe4d735960aebe47f Signed-off-by: Kane Chen Reviewed-on: https://chromium-review.googlesource.com/220742 Reviewed-by: Duncan Laurie [Edit commit message.] Signed-off-by: Paul Menzel Reviewed-on: http://review.coreboot.org/8447 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki Reviewed-by: Stefan Reinauer --- src/include/device/pci_def.h | 2 ++ 1 file changed, 2 insertions(+) (limited to 'src/include/device/pci_def.h') diff --git a/src/include/device/pci_def.h b/src/include/device/pci_def.h index 00d68ad5dc..403978584d 100644 --- a/src/include/device/pci_def.h +++ b/src/include/device/pci_def.h @@ -375,9 +375,11 @@ #define PCI_EXP_LNKCAP_ASPMS 0xc00 /* ASPM Support */ #define PCI_EXP_LNKCAP_L0SEL 0x7000 /* L0s Exit Latency */ #define PCI_EXP_LNKCAP_L1EL 0x38000 /* L1 Exit Latency */ +#define PCI_EXP_CLK_PM 0x40000 /* Clock Power Management */ #define PCI_EXP_LNKCTL 16 /* Link Control */ #define PCI_EXP_LNKCTL_RL 0x20 /* Retrain Link */ #define PCI_EXP_LNKCTL_CCC 0x40 /* Common Clock COnfiguration */ +#define PCI_EXP_EN_CLK_PM 0x100 /* Enable Clock Power Management */ #define PCI_EXP_LNKSTA 18 /* Link Status */ #define PCI_EXP_LNKSTA_LT 0x800 /* Link Training */ #define PCI_EXP_LNKSTA_SLC 0x1000 /* Slot Clock Configuration */ -- cgit v1.2.3