From 8a41f4b71e883ec66be511cb592ee19dfa6708c5 Mon Sep 17 00:00:00 2001 From: Kyösti Mälkki Date: Fri, 8 Feb 2019 18:14:34 +0200 Subject: device/pci_ops: Move questionable pci_locate() variants MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit These are defined for __SIMPLE_DEVICE__ when PCI enumeration has not happened yet. These should not really try to probe devices other than those on bus 0. It's hard to track but there maybe cases of southbridge being located on bus 2 and available for configuration, so I rather leave the code unchanged. Just move these out of arch/io.h because they cause build failures if one attempts to include before . There are two direct copies for ROMCC bootblocks to avoid inlining them elsewhere. Change-Id: Ida2919a5d83fe5ea89284ffbd8ead382e4312524 Signed-off-by: Kyösti Mälkki Reviewed-on: https://review.coreboot.org/c/31304 Tested-by: build bot (Jenkins) Reviewed-by: Arthur Heymans --- src/include/device/pci.h | 6 ++++++ 1 file changed, 6 insertions(+) (limited to 'src/include/device/pci.h') diff --git a/src/include/device/pci.h b/src/include/device/pci.h index f0724e0f99..71d6b2025a 100644 --- a/src/include/device/pci.h +++ b/src/include/device/pci.h @@ -133,6 +133,12 @@ static inline const struct pci_operations *ops_pci(struct device *dev) return pops; } +#define PCI_ID(VENDOR_ID, DEVICE_ID) \ + ((((DEVICE_ID) & 0xFFFF) << 16) | ((VENDOR_ID) & 0xFFFF)) + +pci_devfn_t pci_locate_device(unsigned int pci_id, pci_devfn_t dev); +pci_devfn_t pci_locate_device_on_bus(unsigned int pci_id, unsigned int bus); + #ifdef __SIMPLE_DEVICE__ unsigned int pci_find_next_capability(pci_devfn_t dev, unsigned int cap, unsigned int last); -- cgit v1.2.3