From ebf142a12ce4911b766bd618483434519efba0d5 Mon Sep 17 00:00:00 2001 From: Aaron Durbin Date: Fri, 29 Mar 2013 16:23:23 -0500 Subject: boot: add disable_cache_rom() function On certain architectures such as x86 the bootstrap processor does most of the work. When CACHE_ROM is employed it's appropriate to ensure that the caching enablement of the ROM is disabled so that the caching settings are symmetric before booting the payload or OS. Tested this on an x86 machine that turned on ROM caching. Linux did not complain about asymmetric MTRR settings nor did the ROM show up as cached in the MTRR settings. Change-Id: Ia32ff9fdb1608667a0e9a5f23b9c8af27d589047 Signed-off-by: Aaron Durbin Reviewed-on: http://review.coreboot.org/2980 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer --- src/include/cpu/cpu.h | 3 +++ 1 file changed, 3 insertions(+) (limited to 'src/include/cpu') diff --git a/src/include/cpu/cpu.h b/src/include/cpu/cpu.h index bed77de017..a2272f3e84 100644 --- a/src/include/cpu/cpu.h +++ b/src/include/cpu/cpu.h @@ -9,6 +9,9 @@ struct bus; void initialize_cpus(struct bus *cpu_bus); void asmlinkage secondary_cpu_init(unsigned int cpu_index); +/* If a ROM cache was set up disable it before jumping to the payload or OS. */ +void __attribute__((weak)) disable_cache_rom(void); + #if CONFIG_HAVE_SMI_HANDLER void smm_init(void); void smm_lock(void); -- cgit v1.2.3