From eaaa549e4a176637198f50570b81ecd3a7cf9549 Mon Sep 17 00:00:00 2001 From: Arthur Heymans Date: Wed, 28 Oct 2020 19:30:36 +0100 Subject: cpu/x86/mtrr.h: Rename CORE2 alternative SMRR registers It is too easy to confuse those with IA32_SMRR_PHYS_x registers. Change-Id: Ice02ab6c0315a2be14ef110ede506262e3c0a4d5 Signed-off-by: Arthur Heymans Reviewed-on: https://review.coreboot.org/c/coreboot/+/46896 Reviewed-by: Angel Pons Tested-by: build bot (Jenkins) --- src/include/cpu/x86/mtrr.h | 7 ++++--- 1 file changed, 4 insertions(+), 3 deletions(-) (limited to 'src/include/cpu') diff --git a/src/include/cpu/x86/mtrr.h b/src/include/cpu/x86/mtrr.h index 3bf8301cfd..b8d15179e9 100644 --- a/src/include/cpu/x86/mtrr.h +++ b/src/include/cpu/x86/mtrr.h @@ -31,9 +31,10 @@ #define IA32_SMRR_PHYS_MASK 0x1f3 #define SMRR_PHYS_MASK_LOCK (1 << 10) -/* Specific to model_6fx and model_1067x */ -#define MSR_SMRR_PHYS_BASE 0xa0 -#define MSR_SMRR_PHYS_MASK 0xa1 +/* Specific to model_6fx and model_1067x. + These are named MSR_SMRR_PHYSBASE in the SDM. */ +#define CORE2_SMRR_PHYS_BASE 0xa0 +#define CORE2_SMRR_PHYS_MASK 0xa1 #define MTRR_PHYS_BASE(reg) (0x200 + 2 * (reg)) #define MTRR_PHYS_MASK(reg) (MTRR_PHYS_BASE(reg) + 1) -- cgit v1.2.3