From ad87a82ca7d960ee696dd57c013d75609212eb66 Mon Sep 17 00:00:00 2001 From: Subrata Banik Date: Sat, 31 Dec 2022 14:43:57 +0530 Subject: =?UTF-8?q?security/intel/txt:=20Add=20helper=20function=20to=20di?= =?UTF-8?q?sable=C2=A0TXT?= MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Add a function to disable TXT as per TXT BIOS spec Section 6.2.5. AP firmware can disable TXT if TXT fails or TPM is already enabled. On platforms with TXT disabled, the memory can be unlocked using MSR 0x2e6. TEST=Able to perform disable_txt on SoC SKUs with TXT enabled. Signed-off-by: Subrata Banik Change-Id: I27f613428e82a1dd924172eab853d2ce9c32b473 Reviewed-on: https://review.coreboot.org/c/coreboot/+/71574 Tested-by: build bot (Jenkins) Reviewed-by: Tarun Tuli Reviewed-by: Sridhar Siricilla Reviewed-by: Eric Lai --- src/include/cpu/x86/msr.h | 1 + 1 file changed, 1 insertion(+) (limited to 'src/include/cpu') diff --git a/src/include/cpu/x86/msr.h b/src/include/cpu/x86/msr.h index 33eb457f1a..d369972908 100644 --- a/src/include/cpu/x86/msr.h +++ b/src/include/cpu/x86/msr.h @@ -81,6 +81,7 @@ #define MCA_STATUS_LO_ERRCODE_EXT_SH 16 #define MCA_STATUS_LO_ERRCODE_EXT_MASK (0x3f << MCA_STATUS_LO_ERRCODE_EXT_SH) #define MCA_STATUS_LO_ERRCODE_MASK (0xffff << 0) +#define IA32_LT_UNLOCK_MEMORY 0x2e6 #define IA32_MC0_ADDR 0x402 #define IA32_MC_ADDR(bank) (IA32_MC0_ADDR + 4 * (bank)) #define IA32_MC0_MISC 0x403 -- cgit v1.2.3