From 6a566d7fbee8e81fa22916a29339e5991872edfb Mon Sep 17 00:00:00 2001 From: Lee Leahy Date: Tue, 7 Mar 2017 17:45:12 -0800 Subject: src/include: Wrap lines at 80 columns Fix the following warning detected by checkpatch.pl: WARNING: line over 80 characters Changed a few comments to reduce line length. File src/include/cpu/amd/vr.h was skipped. TEST=Build and run on Galileo Gen2 Change-Id: Ie3c07111acc1f89923fb31135684a6d28a505b61 Signed-off-by: Lee Leahy Reviewed-on: https://review.coreboot.org/18687 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth --- src/include/cpu/amd/amdfam10_sysconf.h | 6 +- src/include/cpu/amd/gx2def.h | 103 ++++++++++++++++++-------------- src/include/cpu/amd/lxdef.h | 105 +++++++++++++++++++-------------- src/include/cpu/amd/model_fxx_rev.h | 3 +- src/include/cpu/amd/msr.h | 3 +- src/include/cpu/amd/mtrr.h | 3 +- src/include/cpu/amd/powernow.h | 3 +- src/include/cpu/intel/l2_cache.h | 6 +- src/include/cpu/x86/lapic.h | 12 ++-- src/include/cpu/x86/msr.h | 6 +- src/include/cpu/x86/mtrr.h | 3 +- src/include/cpu/x86/smm.h | 6 +- 12 files changed, 153 insertions(+), 106 deletions(-) (limited to 'src/include/cpu') diff --git a/src/include/cpu/amd/amdfam10_sysconf.h b/src/include/cpu/amd/amdfam10_sysconf.h index bff65ec917..a60dae3c99 100644 --- a/src/include/cpu/amd/amdfam10_sysconf.h +++ b/src/include/cpu/amd/amdfam10_sysconf.h @@ -40,7 +40,8 @@ struct amdfam10_sysconf_t { unsigned int nodes; unsigned int ht_c_num; // we only can have 32 ht chain at most - unsigned int ht_c_conf_bus[HC_NUMS]; // 4-->32: 4:segn, 8:bus_max, 8:bus_min, 4:linkn, 6: nodeid, 2: enable + // 4-->32: 4:segn, 8:bus_max, 8:bus_min, 4:linkn, 6: nodeid, 2: enable + unsigned int ht_c_conf_bus[HC_NUMS]; unsigned int io_addr_num; unsigned int conf_io_addr[HC_NUMS]; unsigned int conf_io_addrx[HC_NUMS]; @@ -50,7 +51,8 @@ struct amdfam10_sysconf_t { unsigned int segbit; unsigned int hcdn_reg[HC_NUMS]; // it will be used by get_pci1234 - msr_t msr_pstate[NODE_NUMS * 5]; // quad cores all cores in one node should be the same, and p0,..p5 + // quad cores all cores in one node should be the same, and p0,..p5 + msr_t msr_pstate[NODE_NUMS * 5]; unsigned int needs_update_pstate_msrs; unsigned int bsp_apicid; diff --git a/src/include/cpu/amd/gx2def.h b/src/include/cpu/amd/gx2def.h index 6a40d62e4b..330da8526e 100644 --- a/src/include/cpu/amd/gx2def.h +++ b/src/include/cpu/amd/gx2def.h @@ -78,10 +78,14 @@ #define GL1_PCI 4 #define GL1_FG 5 -#define MSR_GLIU0 ((GL0_GLIU0 << 29) + (1 << 28)) /* 1000xxxx - To get on GeodeLink one bit has to be set */ +/* 1000xxxx - To get on GeodeLink one bit has to be set */ +#define MSR_GLIU0 ((GL0_GLIU0 << 29) + (1 << 28)) #define MSR_MC (GL0_MC << 29) /* 2000xxxx */ #define MSR_GLIU1 (GL0_GLIU1 << 29) /* 4000xxxx */ -#define MSR_CPU (GL0_CPU << 29) /* 6000xxxx - this is not used for BIOS since code executing on CPU doesn't need to be routed */ +/* 6000xxxx - this is not used for BIOS since code executing on CPU doesn't + * need to be routed + */ +#define MSR_CPU (GL0_CPU << 29) #define MSR_VG (GL0_VG << 29) /* 8000xxxx */ #define MSR_GP (GL0_GP << 29) /* A000xxxx */ #define MSR_DF (GL0_DF << 29) /* C000xxxx */ @@ -293,7 +297,7 @@ #define RSTPLL_UPPER_VDIV_SHIFT 6 #define RSTPLL_UPPER_FBDIV_SHIFT 0 #define RSTPLL_LOWER_SWFLAGS_SHIFT 26 -#define RSTPLL_LOWER_SWFLAGS_MASK (0x3F<, Raptor Engineering + * Copyright (C) 2015 Timothy Pearson , + * Raptor Engineering * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/include/cpu/amd/mtrr.h b/src/include/cpu/amd/mtrr.h index 8099a3d1fe..b65c23b83a 100644 --- a/src/include/cpu/amd/mtrr.h +++ b/src/include/cpu/amd/mtrr.h @@ -53,7 +53,8 @@ static inline __attribute__((always_inline)) msr_t rdmsr_amd(unsigned int index) return result; } -static inline __attribute__((always_inline)) void wrmsr_amd(unsigned int index, msr_t msr) +static inline __attribute__((always_inline)) void wrmsr_amd(unsigned int index, + msr_t msr) { __asm__ __volatile__ ( "wrmsr" diff --git a/src/include/cpu/amd/powernow.h b/src/include/cpu/amd/powernow.h index 63968151b0..77df7b031e 100644 --- a/src/include/cpu/amd/powernow.h +++ b/src/include/cpu/amd/powernow.h @@ -2,7 +2,8 @@ * This file is part of the coreboot project. * * Copyright (C) 2009 Rudolf Marek - * Copyright (C) 2015 Timothy Pearson , Raptor Engineering + * Copyright (C) 2015 Timothy Pearson , + * Raptor Engineering * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/include/cpu/intel/l2_cache.h b/src/include/cpu/intel/l2_cache.h index 587e43369f..35059ff74f 100644 --- a/src/include/cpu/intel/l2_cache.h +++ b/src/include/cpu/intel/l2_cache.h @@ -83,10 +83,12 @@ #define L2CMD_MESI_I 0 extern int calculate_l2_latency(void); -extern int signal_l2(u32 address_low, u32 data_high, u32 data_low, int way, u8 command); +extern int signal_l2(u32 address_low, u32 data_high, u32 data_low, int way, + u8 command); extern int read_l2(u32 address); extern int write_l2(u32 address, u32 data); -extern int test_l2_address_alias(u32 address1, u32 address2, u32 data_high, u32 data_low); +extern int test_l2_address_alias(u32 address1, u32 address2, u32 data_high, + u32 data_low); extern int calculate_l2_cache_size(void); extern int calculate_l2_physical_address_range(void); extern int set_l2_ecc(void); diff --git a/src/include/cpu/x86/lapic.h b/src/include/cpu/x86/lapic.h index f965bae8c7..6f3cbdb2c1 100644 --- a/src/include/cpu/x86/lapic.h +++ b/src/include/cpu/x86/lapic.h @@ -13,12 +13,14 @@ # define NEED_LAPIC 0 #endif -static inline __attribute__((always_inline)) unsigned long lapic_read(unsigned long reg) +static inline __attribute__((always_inline)) unsigned long lapic_read( + unsigned long reg) { return *((volatile unsigned long *)(LAPIC_DEFAULT_BASE+reg)); } -static inline __attribute__((always_inline)) void lapic_write(unsigned long reg, unsigned long v) +static inline __attribute__((always_inline)) void lapic_write(unsigned long reg, + unsigned long v) { *((volatile unsigned long *)(LAPIC_DEFAULT_BASE+reg)) = v; } @@ -67,7 +69,8 @@ void stop_this_cpu(void); #if !defined(__PRE_RAM__) -#define xchg(ptr, v) ((__typeof__(*(ptr)))__xchg((unsigned long)(v), (ptr), sizeof(*(ptr)))) +#define xchg(ptr, v) ((__typeof__(*(ptr)))__xchg((unsigned long)(v), (ptr), \ + sizeof(*(ptr)))) struct __xchg_dummy { unsigned long a[100]; }; #define __xg(x) ((struct __xchg_dummy *)(x)) @@ -77,7 +80,8 @@ struct __xchg_dummy { unsigned long a[100]; }; * Note 2: xchg has side effect, so that attribute volatile is necessary, * but generally the primitive is invalid, *ptr is output argument. --ANK */ -static inline unsigned long __xchg(unsigned long x, volatile void *ptr, int size) +static inline unsigned long __xchg(unsigned long x, volatile void *ptr, + int size) { switch (size) { case 1: diff --git a/src/include/cpu/x86/msr.h b/src/include/cpu/x86/msr.h index 1175f3b1ba..8070000322 100644 --- a/src/include/cpu/x86/msr.h +++ b/src/include/cpu/x86/msr.h @@ -37,7 +37,8 @@ static inline __attribute__((always_inline)) msr_t rdmsr(unsigned int index) return soc_msr_read(index); } -static inline __attribute__((always_inline)) void wrmsr(unsigned int index, msr_t msr) +static inline __attribute__((always_inline)) void wrmsr(unsigned int index, + msr_t msr) { soc_msr_write(index, msr); } @@ -64,7 +65,8 @@ static inline __attribute__((always_inline)) msr_t rdmsr(unsigned int index) return result; } -static inline __attribute__((always_inline)) void wrmsr(unsigned int index, msr_t msr) +static inline __attribute__((always_inline)) void wrmsr(unsigned int index, + msr_t msr) { __asm__ __volatile__ ( "wrmsr" diff --git a/src/include/cpu/x86/mtrr.h b/src/include/cpu/x86/mtrr.h index 99715ed4e6..36b5c712d9 100644 --- a/src/include/cpu/x86/mtrr.h +++ b/src/include/cpu/x86/mtrr.h @@ -147,7 +147,8 @@ static inline unsigned int fls(unsigned int x) # define CACHE_ROM_SIZE CONFIG_ROM_SIZE # else # define CACHE_ROM_SIZE _ALIGN_UP_POW2(CONFIG_ROM_SIZE) -# if (CACHE_ROM_SIZE < CONFIG_ROM_SIZE) || (CACHE_ROM_SIZE >= (2 * CONFIG_ROM_SIZE)) +# if (CACHE_ROM_SIZE < CONFIG_ROM_SIZE) || (CACHE_ROM_SIZE >= \ + (2 * CONFIG_ROM_SIZE)) # error "CACHE_ROM_SIZE is not optimal." # endif # endif diff --git a/src/include/cpu/x86/smm.h b/src/include/cpu/x86/smm.h index 48c4c0ba01..1892119d53 100644 --- a/src/include/cpu/x86/smm.h +++ b/src/include/cpu/x86/smm.h @@ -474,8 +474,10 @@ void northbridge_smi_handler(void); void southbridge_smi_handler(void); #else void cpu_smi_handler(unsigned int node, smm_state_save_area_t *state_save); -void northbridge_smi_handler(unsigned int node, smm_state_save_area_t *state_save); -void southbridge_smi_handler(unsigned int node, smm_state_save_area_t *state_save); +void northbridge_smi_handler(unsigned int node, + smm_state_save_area_t *state_save); +void southbridge_smi_handler(unsigned int node, + smm_state_save_area_t *state_save); #endif /* CONFIG_SMM_TSEG */ void mainboard_smi_gpi(u32 gpi_sts); int mainboard_smi_apmc(u8 data); -- cgit v1.2.3