From 5bb9fd6e4dae32f86a07676228034d3828820037 Mon Sep 17 00:00:00 2001 From: Kevin O'Connor Date: Wed, 19 Jan 2011 06:32:35 +0000 Subject: Now that the VIA code is run above 1Meg (like other boards), it should cache that range instead of the first 1Meg. This reduces boot time by about 1 second on epia-cn. This patch also adds a MTRRphysMaskValid bit definition. Signed-off-by: Kevin O'Connor Acked-by: Stefan Reinauer git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6272 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1 --- src/include/cpu/x86/mtrr.h | 2 ++ 1 file changed, 2 insertions(+) (limited to 'src/include/cpu') diff --git a/src/include/cpu/x86/mtrr.h b/src/include/cpu/x86/mtrr.h index 164d79af2a..f9aadc58a5 100644 --- a/src/include/cpu/x86/mtrr.h +++ b/src/include/cpu/x86/mtrr.h @@ -21,6 +21,8 @@ #define MTRRphysBase_MSR(reg) (0x200 + 2 * (reg)) #define MTRRphysMask_MSR(reg) (0x200 + 2 * (reg) + 1) +#define MTRRphysMaskValid (1 << 11) + #define NUM_FIXED_RANGES 88 #define MTRRfix64K_00000_MSR 0x250 #define MTRRfix16K_80000_MSR 0x258 -- cgit v1.2.3