From 59ba228f921169bb12347932237c7500ccd58b41 Mon Sep 17 00:00:00 2001 From: Richard Smith Date: Fri, 25 Aug 2006 05:01:30 +0000 Subject: - Added suport for enabling USB P4 on the olpc USB P4 is disabled by default and we need to setup the mux bits proper to make it work. This is the frame work for that. All thats needed is the right address values git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2387 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1 --- src/include/cpu/amd/gx2def.h | 10 +++++++--- 1 file changed, 7 insertions(+), 3 deletions(-) (limited to 'src/include/cpu') diff --git a/src/include/cpu/amd/gx2def.h b/src/include/cpu/amd/gx2def.h index 8e64659120..06f9a6372b 100644 --- a/src/include/cpu/amd/gx2def.h +++ b/src/include/cpu/amd/gx2def.h @@ -731,10 +731,14 @@ /* */ /* USB2*/ /* */ -#define USB2_SB_GLD_MSR_CAP ( MSR_SB_USB2 + 0x00) -#define USB2_SB_GLD_MSR_CONF ( MSR_SB_USB2 + 0x01) -#define USB2_SB_GLD_MSR_PM ( MSR_SB_USB2 + 0x04) +#define USB2_SB_GLD_MSR_CAP ( MSR_SB_USB2 + 0x00) +#define USB2_SB_GLD_MSR_CONF ( MSR_SB_USB2 + 0x01) +#define USB2_SB_GLD_MSR_PM ( MSR_SB_USB2 + 0x04) +#define USB2_SB_GLD_MSR_OHCI_BASE ( MSR_SB_USB2 + 0x08) +#define USB2_SB_GLD_MSR_EHCI_BASE ( MSR_SB_USB2 + 0x09) +#define USB2_SB_GLD_MSR_DEVCTL_BASE ( MSR_SB_USB2 + 0x0A) +#define USB2_SB_GLD_MSR_UOC_BASE ( MSR_SB_USB2 + 0x0B) /* Option controller base */ /* */ /* ATA*/ -- cgit v1.2.3