From 357cc6552ab6f0202c329e9565b278366e2494b8 Mon Sep 17 00:00:00 2001 From: Felix Held Date: Thu, 9 Jul 2020 00:04:22 +0200 Subject: include/cpu/amd/msr: move SMM_LOCK bit right after HWCR_MSR definition MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The SMM_LOCK bit isn't in SMM_MASK_MSR, but in HWCR_MSR, so move it there. The soc/amd/* code itself uses the bit definition when accessing HWCR_MSR, so SMM_LOCK was just below the wrong MSR definition. Also remove SMM_LOCK from comment about masking bits in SMM_MASK_MSR, since that bit isn't in that MSR. TEST=Checked the code and the corresponding BKDG/PPR. Change-Id: I2df446f5a9e11e1e7c8d10256f3c2803b18f9088 Signed-off-by: Felix Held Reviewed-on: https://review.coreboot.org/c/coreboot/+/43309 Reviewed-by: Raul Rangel Reviewed-by: Kyösti Mälkki Tested-by: build bot (Jenkins) --- src/include/cpu/amd/msr.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'src/include/cpu') diff --git a/src/include/cpu/amd/msr.h b/src/include/cpu/amd/msr.h index e466e7bbf2..8bc00d1624 100644 --- a/src/include/cpu/amd/msr.h +++ b/src/include/cpu/amd/msr.h @@ -17,6 +17,7 @@ #define MC4_MISC2 0xC0000409 #define FS_Base 0xC0000100 #define HWCR_MSR 0xC0010015 +#define SMM_LOCK (1 << 0) #define NB_CFG_MSR 0xC001001f #define FidVidStatus 0xC0010042 #define MC1_CTL_MASK 0xC0010045 @@ -53,7 +54,6 @@ #define SMM_BASE_MSR 0xC0010111 #define SMM_ADDR_MSR 0xC0010112 #define SMM_MASK_MSR 0xC0010113 -#define SMM_LOCK (1 << 0) #define SMM_TSEG_VALID (1 << 1) #define SMM_TSEG_WB (6 << 12) -- cgit v1.2.3