From 1c3c0faabc220ef4fc921d9d1dbddb125198abab Mon Sep 17 00:00:00 2001 From: Stefan Reinauer Date: Wed, 19 May 2010 18:39:23 +0000 Subject: cosmetic comment changes. Signed-off-by: Stefan Reinauer Acked-by: Stefan Reinauer git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5572 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1 --- src/include/cpu/x86/cache.h | 17 ++++++++--------- 1 file changed, 8 insertions(+), 9 deletions(-) (limited to 'src/include/cpu') diff --git a/src/include/cpu/x86/cache.h b/src/include/cpu/x86/cache.h index ae61b55b3d..65979fff77 100644 --- a/src/include/cpu/x86/cache.h +++ b/src/include/cpu/x86/cache.h @@ -20,18 +20,17 @@ #ifndef CPU_X86_CACHE #define CPU_X86_CACHE -/* the memory clobber prevents the GCC from reordering the read/write order - of CR0 */ - -#if defined(__GNUC__) - /* -Need this because ROMCC fails here with: + * Need two versions because ROMCC chokes on certain clobbers: + * cache.h:29.71: cache.h:60.24: earlymtrr.c:117.23: romstage.c:144.33: + * 0x1559920 asm Internal compiler error: lhs 1 regcm == 0 + */ -cache.h:29.71: cache.h:60.24: earlymtrr.c:117.23: romstage.c:144.33: -0x1559920 asm Internal compiler error: lhs 1 regcm == 0 -*/ +#if defined(__GNUC__) +/* The memory clobber prevents the GCC from reordering the read/write order + * of CR0 + */ static inline unsigned long read_cr0(void) { unsigned long cr0; -- cgit v1.2.3