From 06f818c932be5e19176db0d50939ee89da3267ad Mon Sep 17 00:00:00 2001 From: Arthur Heymans Date: Fri, 20 Jul 2018 23:41:54 +0200 Subject: cpu/intel/smm/gen1: Use correct MSR for model_6fx and model_1067x MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit According to the "Intel® 64 and IA-32 Architectures Software Developer’s Manual" the SMRR MSR are at a different offset for model_6fx and model_1067x. This still need SMRR enabled and lock bit set in MSR_FEATURE_CONTROL. Change-Id: I8ee8292ab038e58deb8c24745ec1a9b5da8c31a9 Signed-off-by: Arthur Heymans Reviewed-on: https://review.coreboot.org/27585 Tested-by: build bot (Jenkins) Reviewed-by: Felix Held --- src/include/cpu/x86/mtrr.h | 4 ++++ 1 file changed, 4 insertions(+) (limited to 'src/include/cpu/x86') diff --git a/src/include/cpu/x86/mtrr.h b/src/include/cpu/x86/mtrr.h index a4f1f888e3..1f704ac869 100644 --- a/src/include/cpu/x86/mtrr.h +++ b/src/include/cpu/x86/mtrr.h @@ -31,6 +31,10 @@ #define IA32_SMRR_PHYS_BASE 0x1f2 #define IA32_SMRR_PHYS_MASK 0x1f3 +/* Specific to model_6fx and model_1067x */ +#define MSR_SMRR_PHYS_BASE 0xa0 +#define MSR_SMRR_PHYS_MASK 0xa1 + #define MTRR_PHYS_BASE(reg) (0x200 + 2 * (reg)) #define MTRR_PHYS_MASK(reg) (MTRR_PHYS_BASE(reg) + 1) #define MTRR_PHYS_MASK_VALID (1 << 11) -- cgit v1.2.3