From 3aa067f595115a62afdfc9acc33f08e9c96da850 Mon Sep 17 00:00:00 2001 From: Stefan Reinauer Date: Mon, 2 Apr 2012 13:24:04 -0700 Subject: Add support to run SMM handler in TSEG instead of ASEG Traditionally coreboot's SMM handler runs in ASEG (0xa0000), "behind" the graphics memory. This approach has two issues: - It limits the possible size of the SMM handler (and the number of CPUs supported in a system) - It's not considered a supported path anymore in newer CPUs. Change-Id: I9f2877e46873ab2ea8f1157ead4bc644a50be19e Signed-off-by: Duncan Laurie Acked-by: Stefan Reinauer Reviewed-on: http://review.coreboot.org/842 Reviewed-by: Peter Stuge Tested-by: build bot (Jenkins) --- src/include/cpu/x86/smm.h | 2 ++ 1 file changed, 2 insertions(+) (limited to 'src/include/cpu/x86/smm.h') diff --git a/src/include/cpu/x86/smm.h b/src/include/cpu/x86/smm.h index c314c3971a..60959f52f6 100644 --- a/src/include/cpu/x86/smm.h +++ b/src/include/cpu/x86/smm.h @@ -280,6 +280,8 @@ void __attribute__((weak)) southbridge_smi_handler(unsigned int node, smm_state_ void __attribute__((weak)) mainboard_smi_gpi(u16 gpi_sts); int __attribute__((weak)) mainboard_apm_cnt(u8 data); +#if !CONFIG_SMM_TSEG void smi_release_lock(void); +#endif #endif -- cgit v1.2.3