From 918535a657b4ee393708640aa2e8ed3c75de20b9 Mon Sep 17 00:00:00 2001 From: Elyes HAOUAS Date: Thu, 28 Jul 2016 21:25:21 +0200 Subject: src/include: Capitalize CPU, RAM and ROM Change-Id: Id40c1bf868820c77ea20146d19c6d552c2f970c4 Signed-off-by: Elyes HAOUAS Reviewed-on: https://review.coreboot.org/15942 Tested-by: build bot (Jenkins) Reviewed-by: Omar Pakker Reviewed-by: Martin Roth --- src/include/cpu/x86/mtrr.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'src/include/cpu/x86/mtrr.h') diff --git a/src/include/cpu/x86/mtrr.h b/src/include/cpu/x86/mtrr.h index d09c77e2af..f32bececfd 100644 --- a/src/include/cpu/x86/mtrr.h +++ b/src/include/cpu/x86/mtrr.h @@ -91,7 +91,7 @@ int get_free_var_mtrr(void); (x>>6)|(x>>7)|(x>>8)|((1<<18)-1)) #define _ALIGN_UP_POW2(x) ((x + _POW2_MASK(x)) & ~_POW2_MASK(x)) -/* At the end of romstage, low ram 0..CACHE_TM_RAMTOP may be set +/* At the end of romstage, low RAM 0..CACHE_TM_RAMTOP may be set * as write-back cacheable to speed up ramstage decompression. * Note MTRR boundaries, must be power of two. */ -- cgit v1.2.3