From 400ce55566caa541304b2483e61bcc2df941998c Mon Sep 17 00:00:00 2001
From: Elyes HAOUAS <ehaouas@noos.fr>
Date: Fri, 12 Oct 2018 10:54:30 +0200
Subject: cpu/amd: Use common AMD's MSR

Phase 1. Due to the size of the effort, this CL is broken into several
phases.

Change-Id: I0236e0960cd1e79558ea50c814e1de2830aa0550
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/29065
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
---
 src/include/cpu/x86/msr.h | 2 ++
 1 file changed, 2 insertions(+)

(limited to 'src/include/cpu/x86/msr.h')

diff --git a/src/include/cpu/x86/msr.h b/src/include/cpu/x86/msr.h
index 62e56b7a28..032ce4ecb6 100644
--- a/src/include/cpu/x86/msr.h
+++ b/src/include/cpu/x86/msr.h
@@ -25,6 +25,8 @@
 #define IA32_MPERF			0xe7
 #define IA32_APERF			0xe8
 #define IA32_MCG_CAP			0x179
+#define  MCG_CTL_P			(1 << 3)
+#define  MCA_BANKS_MASK			0xff
 #define IA32_PERF_STATUS		0x198
 #define IA32_PERF_CTL			0x199
 #define IA32_THERM_INTERRUPT		0x19b
-- 
cgit v1.2.3