From 3a96074441c4e2b28d6d6961b94fec5c4eada8ec Mon Sep 17 00:00:00 2001 From: Sergii Dmytruk Date: Sat, 21 Aug 2021 16:24:02 +0300 Subject: src/arch/ppc64/*: pass FDT address to payload MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit It's available in %r3 in bootblock and needs to be passed to payload in %r27. We use one of two hypervisor's special registers as a buffer, which aren't used for anything by the code. Change-Id: I0911f4b534c6f8cacfa057a5bad7576fec711637 Signed-off-by: Sergii Dmytruk Reviewed-on: https://review.coreboot.org/c/coreboot/+/57084 Tested-by: build bot (Jenkins) Reviewed-by: Michał Żygowski Reviewed-by: Krystian Hebel --- src/include/cpu/power/spr.h | 3 +++ 1 file changed, 3 insertions(+) (limited to 'src/include/cpu/power') diff --git a/src/include/cpu/power/spr.h b/src/include/cpu/power/spr.h index f22a6cab3d..3b229f73a3 100644 --- a/src/include/cpu/power/spr.h +++ b/src/include/cpu/power/spr.h @@ -9,6 +9,9 @@ #define SPR_PVR_REV_MASK (PPC_BITMASK(52, 55) | PPC_BITMASK(60, 63)) #define SPR_PVR_REV(maj, min) (PPC_SHIFT((maj), 55) | PPC_SHIFT((min), 63)) +#define SPR_HSPRG0 0x130 +#define SPR_HSPRG1 0x131 + #define SPR_HRMOR 0x139 #define SPR_HMER 0x150 -- cgit v1.2.3