From 5bc641afebda5fd274ba713add4145651d9bc71d Mon Sep 17 00:00:00 2001 From: Kyösti Mälkki Date: Fri, 9 Aug 2019 09:37:49 +0300 Subject: cpu/intel: Refactor platform_enter_postcar() MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit There are benefits in placing the postcar_frame structure in .bss and returning control to romstage_main(). Change-Id: I0418a2abc74f749203c587b2763c5f8a5960e4f9 Signed-off-by: Kyösti Mälkki Reviewed-on: https://review.coreboot.org/c/coreboot/+/34808 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin --- src/include/cpu/intel/romstage.h | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) (limited to 'src/include/cpu/intel') diff --git a/src/include/cpu/intel/romstage.h b/src/include/cpu/intel/romstage.h index 47cd169e6a..328f464ec4 100644 --- a/src/include/cpu/intel/romstage.h +++ b/src/include/cpu/intel/romstage.h @@ -5,6 +5,10 @@ void mainboard_romstage_entry(unsigned long bist); -void platform_enter_postcar(void); +/* fill_postcar_frame() is called after raminit completes and right before + * calling run_postcar_phase(). Implementation should call postcar_frame_add_mtrr() + * to tag memory ranges as cacheable to speed up execution of postcar and + * early ramstage. */ +void fill_postcar_frame(struct postcar_frame *pcf); #endif /* _CPU_INTEL_ROMSTAGE_H */ -- cgit v1.2.3