From f5d688a5a2bc1d62fb463a76a04267cb349b158f Mon Sep 17 00:00:00 2001
From: Duncan Laurie <dlaurie@google.com>
Date: Mon, 15 Oct 2018 15:22:21 -0700
Subject: ec/google/wilco: Add ACPI SuperIO devices

Add ACPI devices for the basic SuperIO functionality provided by the EC
for PS/2 keyboard, PS/2 mouse (trackpad emulation), and legacy UART.

The specific defines to enable these devices should be declared by the
mainboard before including this ASL, the same as the Chrome EC behavior.

Change-Id: I910940ebf26b8758ab12d695e1eba9c668c640c6
Signed-off-by: Duncan Laurie <dlaurie@google.com>
Reviewed-on: https://review.coreboot.org/29125
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
---
 src/ec/google/wilco/acpi/superio.asl | 117 +++++++++++++++++++++++++++++++++++
 1 file changed, 117 insertions(+)
 create mode 100644 src/ec/google/wilco/acpi/superio.asl

(limited to 'src/ec')

diff --git a/src/ec/google/wilco/acpi/superio.asl b/src/ec/google/wilco/acpi/superio.asl
new file mode 100644
index 0000000000..a8cea7891a
--- /dev/null
+++ b/src/ec/google/wilco/acpi/superio.asl
@@ -0,0 +1,117 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2018 Google LLC
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of
+ * the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+/* Scope is \_SB.PCI0.LPCB */
+
+Device (SIO)
+{
+	Name (_UID, 0)
+	Name (_ADR, 0)
+
+	Device (COM1)
+	{
+		Name (_HID, EisaId ("PNP0501"))
+		Name (_UID, 1)
+		Name (_ADR, 0)
+
+		Method (_STA, 0, NotSerialized)
+		{
+#ifdef SIO_EC_ENABLE_COM1
+			Return (0x0f)
+#else
+			Return (Zero)
+#endif
+		}
+
+		Name (_CRS, ResourceTemplate ()
+		{
+			IO (Decode16, 0x03F8, 0x3F8, 0x08, 0x08)
+			IRQNoFlags () {4}
+		})
+
+		Name (_PRS, ResourceTemplate ()
+		{
+			StartDependentFn (0, 0) {
+				IO (Decode16, 0x03F8, 0x3F8, 0x08, 0x08)
+				IRQNoFlags () {4}
+			}
+			EndDependentFn ()
+		})
+	}
+
+	Device (PS2K)
+	{
+		Name (_HID, EisaId ("PNP0303"))
+		Name (_CID, EisaId ("PNP030B"))
+		Name (_UID, 0)
+		Name (_ADR, 0)
+
+		Method (_STA, 0, NotSerialized)
+		{
+#ifdef SIO_EC_ENABLE_PS2K
+			Return (0x0f)
+#else
+			Return (Zero)
+#endif
+		}
+
+		Name (_CRS, ResourceTemplate()
+		{
+			IO (Decode16, 0x60, 0x60, 0x01, 0x01)
+			IO (Decode16, 0x64, 0x64, 0x01, 0x01)
+			IRQ (Edge, ActiveHigh, Exclusive) {1}
+		})
+
+		Name (_PRS, ResourceTemplate()
+		{
+			StartDependentFn (0, 0) {
+				IO (Decode16, 0x60, 0x60, 0x01, 0x01)
+				IO (Decode16, 0x64, 0x64, 0x01, 0x01)
+				IRQ (Edge, ActiveHigh, Exclusive) {1}
+			}
+			EndDependentFn ()
+		})
+	}
+
+	Device (PS2M)
+	{
+		Name (_HID, EisaId ("PNP0F13"))
+		Name (_UID, 0)
+		Name (_ADR, 0)
+
+		Method (_STA, 0, NotSerialized)
+		{
+#ifdef SIO_EC_ENABLE_PS2M
+			Return (0x0f)
+#else
+			Return (Zero)
+#endif
+		}
+
+		Name (_CRS, ResourceTemplate()
+		{
+			IRQ (Edge, ActiveHigh, Exclusive) {12}
+		})
+
+		Name (_PRS, ResourceTemplate()
+		{
+			StartDependentFn (0, 0) {
+				IRQ (Edge, ActiveHigh, Exclusive) {12}
+			}
+			EndDependentFn ()
+		})
+	}
+}
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