From 366b205f2d9fa2bd8cf4e72da125b5036b7295e0 Mon Sep 17 00:00:00 2001
From: EricKY Cheng <ericky_cheng@compal.corp-partner.google.com>
Date: Fri, 23 Sep 2022 17:04:01 +0800
Subject: ec/google/chromec: Add DPTC support for host event 1/2/9

DTTS is Dynamic Thermal Table Switching Proposal. Add DPTC support for
host event lid-open/lid-close/Thermal Threshold.

BUG=b:232946420
TEST=emerge-skyrim coreboot

Signed-off-by: EricKY Cheng <ericky_cheng@compal.corp-partner.google.com>
Change-Id: I156a9d138ccac7f75cc0dd0d827f7a721fcbc782
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67793
Reviewed-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
---
 src/ec/google/chromeec/acpi/ec.asl | 16 ++++++++++++++++
 1 file changed, 16 insertions(+)

(limited to 'src/ec')

diff --git a/src/ec/google/chromeec/acpi/ec.asl b/src/ec/google/chromeec/acpi/ec.asl
index e4637b3d36..7c252e6c81 100644
--- a/src/ec/google/chromeec/acpi/ec.asl
+++ b/src/ec/google/chromeec/acpi/ec.asl
@@ -229,6 +229,11 @@ Device (EC0)
 	Method (_Q01, 0, NotSerialized)
 	{
 		Printf ("EC: LID CLOSE")
+#if CONFIG(SOC_AMD_COMMON_BLOCK_ACPI_DPTC)
+		If (CondRefOf (\_SB.DPTC)) {
+			\_SB.DPTC()
+		}
+#endif
 		Store (LIDS, \LIDS)
 #ifdef EC_ENABLE_LID_SWITCH
 		Notify (LID0, 0x80)
@@ -239,6 +244,11 @@ Device (EC0)
 	Method (_Q02, 0, NotSerialized)
 	{
 		Printf ("EC: LID OPEN")
+#if CONFIG(SOC_AMD_COMMON_BLOCK_ACPI_DPTC)
+		If (CondRefOf (\_SB.DPTC)) {
+			\_SB.DPTC()
+		}
+#endif
 		Store (LIDS, \LIDS)
 		Notify (CREC, 0x2)
 #ifdef EC_ENABLE_LID_SWITCH
@@ -540,6 +550,12 @@ Device (EC0)
 	 */
 	Method (_Q09, 0, NotSerialized)
 	{
+
+#if CONFIG(SOC_AMD_COMMON_BLOCK_ACPI_DPTC)
+		If (CondRefOf (\_SB.DPTC)) {
+			\_SB.DPTC()
+		}
+#endif
 		If (!Acquire (^PATM, 1000)) {
 			/* Read sensor ID for event */
 			Store (^PATI, Local0)
-- 
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