From 065c5870e4678367f5be7014361772c9d03933c8 Mon Sep 17 00:00:00 2001 From: EricKY Cheng Date: Mon, 3 Oct 2022 16:24:04 +0800 Subject: ec/google/chromec: Expand EC share memory for DTTS DTTS is Dynamic Thermal Table Switching Proposal. DTTS needs one bit to save the body detection result from EC. Define mode change STTB bit for Desktop (1) and laptop (0). This bit is Switch thermal table by body detection status. BUG=b:232946420 TEST=emerge-skyrim coreboot Signed-off-by: EricKY Cheng Change-Id: I37b3a0d8f6546361c8d5501e98e3e1b0d814fce3 Reviewed-on: https://review.coreboot.org/c/coreboot/+/68077 Reviewed-by: Tim Van Patten Reviewed-by: Raul Rangel Tested-by: build bot (Jenkins) --- src/ec/google/chromeec/acpi/ec.asl | 1 + 1 file changed, 1 insertion(+) (limited to 'src/ec/google/chromeec') diff --git a/src/ec/google/chromeec/acpi/ec.asl b/src/ec/google/chromeec/acpi/ec.asl index 0914fdda37..32009028d3 100644 --- a/src/ec/google/chromeec/acpi/ec.asl +++ b/src/ec/google/chromeec/acpi/ec.asl @@ -56,6 +56,7 @@ Device (EC0) CHGL, 8, // Charger Current Limit TBMD, 1, // Tablet mode DDPN, 3, // Device DPTF Profile Number + STTB, 1, // Switch thermal table by body detection status // DFUD must be 0 for the other 31 values to be valid Offset (0x0a), DFUD, 1, // Device Features Undefined -- cgit v1.2.3