From ecf6531c47f77cae0e5d1349319b1f2c997e994f Mon Sep 17 00:00:00 2001 From: Duncan Laurie Date: Wed, 26 Sep 2018 21:11:58 +0000 Subject: ec/google/chromeec: Define a sync IRQ if needed Some boards are adding a second pin used for synchronization between the EC and AP. This is a direct connection between the EC and the SOC that is intended to provide a lower latency interrupt signal for sensors on the EC. Currently the runtime EC interrupts assert an SCI before eventually resulting in a Notify() on the MKBP device that the sensor driver users. These extra layers add processing time and require additional EC communication to determine the event source. This interface was tested on a reworked Nocturne board with modified EC and a modified kernel driver to ensure that the interrupt asserts as expected and can be used by the kernel driver. Change-Id: I49a11363ce82882e572bcb8923fd114ab6593fea Signed-off-by: Duncan Laurie Reviewed-on: https://review.coreboot.org/28758 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh --- src/ec/google/chromeec/acpi/cros_ec.asl | 10 ++++++++++ 1 file changed, 10 insertions(+) (limited to 'src/ec/google/chromeec/acpi') diff --git a/src/ec/google/chromeec/acpi/cros_ec.asl b/src/ec/google/chromeec/acpi/cros_ec.asl index d0a5b68438..befd5a73c2 100644 --- a/src/ec/google/chromeec/acpi/cros_ec.asl +++ b/src/ec/google/chromeec/acpi/cros_ec.asl @@ -22,6 +22,16 @@ Device (CREC) Name (_PRW, Package () { EC_ENABLE_WAKE_PIN, 0x5 }) #endif +#ifdef EC_ENABLE_SYNC_IRQ + Name (_CRS, ResourceTemplate () + { + Interrupt (ResourceConsumer, Edge, ActiveLow, Exclusive) + { + EC_SYNC_IRQ + } + }) +#endif + #ifdef EC_ENABLE_MKBP_DEVICE Device (CKSC) { -- cgit v1.2.3