From 2873fd277000cbe48348c92b20bce2eaa7212e10 Mon Sep 17 00:00:00 2001 From: Tim Van Patten Date: Mon, 29 Aug 2022 11:36:35 -0600 Subject: acpi: Replace EC_ENABLE_AMD_DPTC_SUPPORT with Kconfig value Compile-time support of DPTC is controlled by EC_ENABLE_AMD_DPTC_SUPPORT in each variant's ec.h file. This CL removes EC_ENABLE_AMD_DPTC_SUPPORT and replaces it with the Kconfig value SOC_AMD_COMMON_BLOCK_ACPI_DPTC. Each variant's run-time support of DPTC continues to be controlled by the variant's overridetree.cb "dptc_enable" value. BRANCH=none BUG=b:217911928 TEST=Build zork TEST=Boot skyrim Signed-off-by: Tim Van Patten Change-Id: Ic101e74bab88e20be0cb5aaf66e4349baa1432e3 Reviewed-on: https://review.coreboot.org/c/coreboot/+/67180 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth Reviewed-by: Raul Rangel --- src/ec/google/chromeec/acpi/ec.asl | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) (limited to 'src/ec/google/chromeec/acpi') diff --git a/src/ec/google/chromeec/acpi/ec.asl b/src/ec/google/chromeec/acpi/ec.asl index b85e1861a0..0914fdda37 100644 --- a/src/ec/google/chromeec/acpi/ec.asl +++ b/src/ec/google/chromeec/acpi/ec.asl @@ -17,7 +17,7 @@ External (\_SB.DPTF.TCHG, DeviceObj) #endif /* Enable DPTC interface with AMD ALIB */ -#ifdef EC_ENABLE_AMD_DPTC_SUPPORT +#if CONFIG(SOC_AMD_COMMON_BLOCK_ACPI_DPTC) External(\_SB.DPTC, MethodObj) #endif @@ -177,7 +177,7 @@ Device (EC0) // Initialize LID switch state Store (LIDS, \LIDS) -#ifdef EC_ENABLE_AMD_DPTC_SUPPORT +#if CONFIG(SOC_AMD_COMMON_BLOCK_ACPI_DPTC) /* * Per the device mode (clamshell or tablet) to initialize * the thermal setting on OS startup. @@ -435,7 +435,7 @@ Device (EC0) #ifdef EC_ENABLE_TBMC_DEVICE Notify (TBMC, 0x80) #endif -#ifdef EC_ENABLE_AMD_DPTC_SUPPORT +#if CONFIG(SOC_AMD_COMMON_BLOCK_ACPI_DPTC) If (CondRefOf (\_SB.DPTC)) { \_SB.DPTC() } -- cgit v1.2.3