From ee2e936f4059d8aad4161d44915a05271df1aaae Mon Sep 17 00:00:00 2001 From: Kyösti Mälkki Date: Fri, 28 Dec 2018 16:06:45 +0200 Subject: arch/x86: Unify bootblock MMX register usage MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Have same usage of registers with romcc bootblock and C_ENVIRONMENT_BOOTBLOCK. Change-Id: Ibfa80e40f0b736a904abf4245fc23efc0cdc458d Signed-off-by: Kyösti Mälkki Reviewed-on: https://review.coreboot.org/c/30490 Tested-by: build bot (Jenkins) Reviewed-by: Arthur Heymans --- src/drivers/intel/fsp1_1/cache_as_ram.inc | 17 +++++++++++++---- 1 file changed, 13 insertions(+), 4 deletions(-) (limited to 'src/drivers') diff --git a/src/drivers/intel/fsp1_1/cache_as_ram.inc b/src/drivers/intel/fsp1_1/cache_as_ram.inc index 934ae670dc..16712133e9 100644 --- a/src/drivers/intel/fsp1_1/cache_as_ram.inc +++ b/src/drivers/intel/fsp1_1/cache_as_ram.inc @@ -29,11 +29,20 @@ #define LHLT_DELAY 0x50000 /* I/O delay between post codes on failure */ /* - * eax: BIST value - * mm0: low 32-bits of TSC value - * mm1: high 32-bits of TSC value + * Per FSP1.1 specs, following registers are preserved: + * EBX, EDI, ESI, EBP, MM0, MM1 + * + * Shift values to release MM2. + * mm0 -> edi: BIST value + * mm1 -> mm0: low 32-bits of TSC value + * mm2 -> mm1: high 32-bits of TSC value */ - movl %eax, %edi + movd %mm0, %edi + movd %mm1, %eax + movd %eax, %mm0 + movd %mm2, %eax + movd %eax, %mm1 + cache_as_ram: post_code(0x20) -- cgit v1.2.3