From 9c0e14e7c43e85e99c0bbfdff72019d908de1711 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Ky=C3=B6sti=20M=C3=A4lkki?= Date: Wed, 23 Jan 2019 16:46:35 +0200 Subject: device/pci_ops: Define pci_find_capability() just once MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Wrap the simple romstage implementation to be called from ramstage. Change-Id: Iadadf3d550416850d6c37233bd4eda025f4d3960 Signed-off-by: Kyösti Mälkki Reviewed-on: https://review.coreboot.org/c/coreboot/+/31755 Reviewed-by: Paul Menzel Reviewed-by: Martin Roth Reviewed-by: HAOUAS Elyes Reviewed-by: Angel Pons Tested-by: build bot (Jenkins) --- src/drivers/usb/pci_ehci.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'src/drivers') diff --git a/src/drivers/usb/pci_ehci.c b/src/drivers/usb/pci_ehci.c index 5621b37da9..34684cb09a 100644 --- a/src/drivers/usb/pci_ehci.c +++ b/src/drivers/usb/pci_ehci.c @@ -49,7 +49,7 @@ int ehci_debug_hw_enable(unsigned int *base, unsigned int *dbg_offset) if (class != PCI_EHCI_CLASSCODE) return -1; - u8 pm_cap = pci_find_capability(dev, PCI_CAP_ID_PM); + u8 pm_cap = pci_s_find_capability(dbg_dev, PCI_CAP_ID_PM); if (pm_cap) { u16 pm_ctrl = pci_read_config16(dev, pm_cap + PCI_PM_CTRL); /* Set to D0 and disable PM events. */ @@ -58,7 +58,7 @@ int ehci_debug_hw_enable(unsigned int *base, unsigned int *dbg_offset) pci_write_config16(dev, pm_cap + PCI_PM_CTRL, pm_ctrl); } - u8 pos = pci_find_capability(dev, PCI_CAP_ID_EHCI_DEBUG); + u8 pos = pci_s_find_capability(dbg_dev, PCI_CAP_ID_EHCI_DEBUG); if (!pos) return -1; -- cgit v1.2.3