From 8465a81e81dfb2ed1fc24b9cf053b09d86fa5163 Mon Sep 17 00:00:00 2001 From: Lijian Zhao Date: Tue, 11 Jul 2017 12:33:22 -0700 Subject: soc/intel/cannonlake: Add postcar stage support Initialize postcar frame once finish FSP memoryinit This patch was merged too early and reverted. Originally reviewed on https://review.coreboot.org/#/c/20534 Change-Id: Id36aa44bb7a89303bc22e92e0313cf685351690a Signed-off-by: Lijian Zhao Reviewed-on: https://review.coreboot.org/20688 Reviewed-by: Aaron Durbin Tested-by: build bot (Jenkins) --- src/drivers/intel/fsp2_0/Makefile.inc | 1 + 1 file changed, 1 insertion(+) (limited to 'src/drivers') diff --git a/src/drivers/intel/fsp2_0/Makefile.inc b/src/drivers/intel/fsp2_0/Makefile.inc index cdf6146d51..d5709adc31 100644 --- a/src/drivers/intel/fsp2_0/Makefile.inc +++ b/src/drivers/intel/fsp2_0/Makefile.inc @@ -43,6 +43,7 @@ postcar-$(CONFIG_CACHE_RELOCATED_RAMSTAGE_OUTSIDE_CBMEM) += stage_cache.c postcar-$(CONFIG_FSP_CAR) += temp_ram_exit.c postcar-$(CONFIG_FSP_CAR) += util.c postcar-$(CONFIG_DISPLAY_FSP_HEADER) += header_display.c +postcar-y += hand_off_block.c CPPFLAGS_common += -I$(src)/drivers/intel/fsp2_0/include -- cgit v1.2.3