From 808c95056604bf4c33cb5f1246273604d83b7069 Mon Sep 17 00:00:00 2001 From: Arthur Heymans Date: Fri, 30 Apr 2021 15:10:52 +0200 Subject: drivers/intel/fsp1_1: Remove verstage compilation units Only SOC_INTEL_BRASWELL is using FSP1.1. It has too little CAR available set up by FSP-T to have VBOOT_STARTS_IN_BOOTBLOCK and therefore verstage is not possible either. Change-Id: I54361c835055907c2a4414ec26a1495425d4ef09 Signed-off-by: Arthur Heymans Reviewed-on: https://review.coreboot.org/c/coreboot/+/52785 Reviewed-by: Angel Pons Reviewed-by: Frans Hendriks Tested-by: build bot (Jenkins) --- src/drivers/intel/fsp1_1/Makefile.inc | 4 ---- src/drivers/intel/fsp1_1/verstage.c | 11 ----------- 2 files changed, 15 deletions(-) delete mode 100644 src/drivers/intel/fsp1_1/verstage.c (limited to 'src/drivers') diff --git a/src/drivers/intel/fsp1_1/Makefile.inc b/src/drivers/intel/fsp1_1/Makefile.inc index 4b8e0a81f0..c890f350e1 100644 --- a/src/drivers/intel/fsp1_1/Makefile.inc +++ b/src/drivers/intel/fsp1_1/Makefile.inc @@ -2,10 +2,6 @@ ifeq ($(CONFIG_PLATFORM_USES_FSP1_1),y) -verstage-y += car.c -verstage-y += fsp_util.c -verstage-$(CONFIG_VBOOT_SEPARATE_VERSTAGE) += verstage.c - bootblock-$(CONFIG_USE_GENERIC_FSP_CAR_INC) += cache_as_ram.S bootblock-y += fsp_util.c bootblock-y += ../../../cpu/intel/microcode/microcode_asm.S diff --git a/src/drivers/intel/fsp1_1/verstage.c b/src/drivers/intel/fsp1_1/verstage.c deleted file mode 100644 index c001b62bdf..0000000000 --- a/src/drivers/intel/fsp1_1/verstage.c +++ /dev/null @@ -1,11 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#include -#include - -void *cache_as_ram_stage_main(FSP_INFO_HEADER *fih) -{ - run_romstage(); - /* Will actually never return. */ - return NULL; -} -- cgit v1.2.3