From 73ac12196c61c8d0c21a54dfa87b858662d6859a Mon Sep 17 00:00:00 2001 From: Arthur Heymans Date: Thu, 23 May 2019 14:41:19 +0200 Subject: drivers/intel/fsp1.1: Simplify bootflow and clean up MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit This gets rid of the boilerplate back and forward calls between the SOC/FSP-driver code and mainboard code. Change-Id: I5d4a10d1da6b3ac5e65efd7f82607b56b80e08d4 Signed-off-by: Arthur Heymans Reviewed-on: https://review.coreboot.org/c/coreboot/+/32961 Reviewed-by: Patrick Georgi Reviewed-by: Frans Hendriks Reviewed-by: Kyösti Mälkki Tested-by: build bot (Jenkins) --- src/drivers/intel/fsp1_1/include/fsp/romstage.h | 4 +- src/drivers/intel/fsp1_1/romstage.c | 91 ++++++++++++------------- 2 files changed, 44 insertions(+), 51 deletions(-) (limited to 'src/drivers') diff --git a/src/drivers/intel/fsp1_1/include/fsp/romstage.h b/src/drivers/intel/fsp1_1/include/fsp/romstage.h index 7efbb1085c..2caceebfa0 100644 --- a/src/drivers/intel/fsp1_1/include/fsp/romstage.h +++ b/src/drivers/intel/fsp1_1/include/fsp/romstage.h @@ -44,15 +44,13 @@ struct romstage_params { void mainboard_memory_init_params(struct romstage_params *params, MEMORY_INIT_UPD *memory_params); -void mainboard_romstage_entry(struct romstage_params *params); +void mainboard_pre_raminit(struct romstage_params *params); void mainboard_save_dimm_info(struct romstage_params *params); void mainboard_add_dimm_info(struct romstage_params *params, struct memory_info *mem_info, int channel, int dimm, int index); void raminit(struct romstage_params *params); void report_memory_config(void); -void romstage_common(struct romstage_params *params); -asmlinkage void romstage_main(FSP_INFO_HEADER *fih); /* Initialize memory margin analysis settings. */ void setup_mma(MEMORY_INIT_UPD *memory_upd); void soc_after_ram_init(struct romstage_params *params); diff --git a/src/drivers/intel/fsp1_1/romstage.c b/src/drivers/intel/fsp1_1/romstage.c index 45ca87aac8..d86d3ab484 100644 --- a/src/drivers/intel/fsp1_1/romstage.c +++ b/src/drivers/intel/fsp1_1/romstage.c @@ -37,48 +37,7 @@ #include #include -asmlinkage void romstage_main(FSP_INFO_HEADER *fih) -{ - struct romstage_params params = { - .chipset_context = fih, - }; - - post_code(0x30); - - timestamp_add_now(TS_START_ROMSTAGE); - - /* Load microcode before RAM init */ - if (CONFIG(SUPPORT_CPU_UCODE_IN_CBFS)) - intel_update_microcode_from_cbfs(); - - /* Display parameters */ - if (!CONFIG(NO_MMCONF_SUPPORT)) - printk(BIOS_SPEW, "CONFIG_MMCONF_BASE_ADDRESS: 0x%08x\n", - CONFIG_MMCONF_BASE_ADDRESS); - printk(BIOS_INFO, "Using FSP 1.1\n"); - - /* Display FSP banner */ - print_fsp_info(fih); - - /* Stash FSP version. */ - params.fsp_version = fsp_version(fih); - - /* Get power state */ - params.power_state = fill_power_state(); - - /* Call into mainboard. */ - mainboard_romstage_entry(¶ms); - soc_after_ram_init(¶ms); - post_code(0x38); -} - -void cache_as_ram_stage_main(FSP_INFO_HEADER *fih) -{ - romstage_main(fih); -} - -/* Entry from the mainboard. */ -void romstage_common(struct romstage_params *params) +static void raminit_common(struct romstage_params *params) { bool s3wake; struct region_device rdev; @@ -153,6 +112,47 @@ void romstage_common(struct romstage_params *params) full_reset(); } +void cache_as_ram_stage_main(FSP_INFO_HEADER *fih) +{ + struct romstage_params params = { + .chipset_context = fih, + }; + + post_code(0x30); + + timestamp_add_now(TS_START_ROMSTAGE); + + /* Load microcode before RAM init */ + if (CONFIG(SUPPORT_CPU_UCODE_IN_CBFS)) + intel_update_microcode_from_cbfs(); + + /* Display parameters */ + if (!CONFIG(NO_MMCONF_SUPPORT)) + printk(BIOS_SPEW, "CONFIG_MMCONF_BASE_ADDRESS: 0x%08x\n", + CONFIG_MMCONF_BASE_ADDRESS); + printk(BIOS_INFO, "Using FSP 1.1\n"); + + /* Display FSP banner */ + print_fsp_info(fih); + + /* Stash FSP version. */ + params.fsp_version = fsp_version(fih); + + /* Get power state */ + params.power_state = fill_power_state(); + + /* Board initialization before and after RAM is enabled */ + mainboard_pre_raminit(¶ms); + + post_code(0x31); + + /* Initialize memory */ + raminit_common(¶ms); + + soc_after_ram_init(¶ms); + post_code(0x38); +} + /* Initialize the power state */ __weak struct chipset_power_state *fill_power_state(void) { @@ -160,13 +160,8 @@ __weak struct chipset_power_state *fill_power_state(void) } /* Board initialization before and after RAM is enabled */ -__weak void mainboard_romstage_entry( - struct romstage_params *params) +__weak void mainboard_pre_raminit(struct romstage_params *params) { - post_code(0x31); - - /* Initialize memory */ - romstage_common(params); } /* Save the DIMM information for SMBIOS table 17 */ -- cgit v1.2.3