From 37b5ef26eb5627ddbae295a1045d174e012fb1cc Mon Sep 17 00:00:00 2001 From: Lee Leahy Date: Sun, 31 Jul 2016 14:15:49 -0700 Subject: drivers/intel/fsp2_0: Disable display of FSP header Add a Kconfig value to enable display of FSP header. Move the display code into a separate module to remove it entirely from the final image. TEST=Build and run on Galileo Gen2 Change-Id: I7047a9e58e6a6481c8453dbfebfbfe69dc8823d8 Signed-off-by: Lee Leahy Reviewed-on: https://review.coreboot.org/16002 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin --- src/drivers/intel/fsp2_0/Kconfig | 6 +++ src/drivers/intel/fsp2_0/Makefile.inc | 2 + src/drivers/intel/fsp2_0/header_display.c | 58 ++++++++++++++++++++++ src/drivers/intel/fsp2_0/include/fsp/debug.h | 1 + src/drivers/intel/fsp2_0/include/fsp/info_header.h | 1 - src/drivers/intel/fsp2_0/util.c | 46 +---------------- 6 files changed, 69 insertions(+), 45 deletions(-) create mode 100644 src/drivers/intel/fsp2_0/header_display.c (limited to 'src/drivers') diff --git a/src/drivers/intel/fsp2_0/Kconfig b/src/drivers/intel/fsp2_0/Kconfig index 4ff6116ee1..729c2f248e 100644 --- a/src/drivers/intel/fsp2_0/Kconfig +++ b/src/drivers/intel/fsp2_0/Kconfig @@ -34,6 +34,12 @@ config DISPLAY_FSP_CALLS_AND_STATUS Display the FSP call entry point and parameters prior to calling FSP and display the status upon return from FSP. +config DISPLAY_FSP_HEADER + bool "Display the FSP header" + default n + help + Display the FSP header information when the FSP file is found. + config DISPLAY_HOBS bool "Display the hand-off-blocks" default n diff --git a/src/drivers/intel/fsp2_0/Makefile.inc b/src/drivers/intel/fsp2_0/Makefile.inc index c42c034152..0a6ae433a0 100644 --- a/src/drivers/intel/fsp2_0/Makefile.inc +++ b/src/drivers/intel/fsp2_0/Makefile.inc @@ -17,6 +17,7 @@ ifeq ($(CONFIG_PLATFORM_USES_FSP2_0),y) romstage-y += debug.c romstage-y += hand_off_block.c +romstage-$(CONFIG_DISPLAY_FSP_HEADER) += header_display.c romstage-$(CONFIG_DISPLAY_HOBS) += hob_display.c romstage-$(CONFIG_DISPLAY_UPD_DATA) += upd_display.c romstage-$(CONFIG_VERIFY_HOBS) += hob_verify.c @@ -26,6 +27,7 @@ romstage-y += memory_init.c ramstage-y += debug.c ramstage-y += graphics.c ramstage-y += hand_off_block.c +ramstage-$(CONFIG_DISPLAY_FSP_HEADER) += header_display.c ramstage-$(CONFIG_DISPLAY_HOBS) += hob_display.c ramstage-$(CONFIG_VERIFY_HOBS) += hob_verify.c ramstage-y += notify.c diff --git a/src/drivers/intel/fsp2_0/header_display.c b/src/drivers/intel/fsp2_0/header_display.c new file mode 100644 index 0000000000..543c075846 --- /dev/null +++ b/src/drivers/intel/fsp2_0/header_display.c @@ -0,0 +1,58 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2015-2016 Intel Corp. + * (Written by Alexandru Gagniuc for Intel Corp.) + * (Written by Andrey Petrov for Intel Corp.) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + */ + +#include +#include + +void fsp_print_header_info(const struct fsp_header *hdr) +{ + union { + uint32_t val; + struct { + uint8_t bld_num; + uint8_t revision; + uint8_t minor; + uint8_t major; + } rev; + } revision; + + revision.val = hdr->fsp_revision; + + printk(BIOS_SPEW, "Spec version: v%u.%u\n", (hdr->spec_version >> 4 ), + hdr->spec_version & 0xf); + printk(BIOS_SPEW, "Revision: %u.%u.%u, Build Number %u\n", + revision.rev.major, + revision.rev.minor, + revision.rev.revision, + revision.rev.bld_num); + printk(BIOS_SPEW, "Type: %s/%s\n", + (hdr->component_attribute & 1 ) ? "release" : "debug", + (hdr->component_attribute & 2 ) ? "test" : "official"); + printk(BIOS_SPEW, "image ID: %s, base 0x%lx + 0x%zx\n", + hdr->image_id, hdr->image_base, hdr->image_size); + printk(BIOS_SPEW, "\tConfig region 0x%zx + 0x%zx\n", + hdr->cfg_region_offset, hdr->cfg_region_size); + + if ((hdr->component_attribute >> 12) == FSP_HDR_ATTRIB_FSPM) { + printk(BIOS_SPEW, "\tMemory init offset 0x%zx\n", + hdr->memory_init_entry_offset); + } + + if ((hdr->component_attribute >> 12) == FSP_HDR_ATTRIB_FSPS) { + printk(BIOS_SPEW, "\tSilicon init offset 0x%zx\n", + hdr->silicon_init_entry_offset); + printk(BIOS_SPEW, "\tNotify phase offset 0x%zx\n", + hdr->notify_phase_entry_offset); + } + +} diff --git a/src/drivers/intel/fsp2_0/include/fsp/debug.h b/src/drivers/intel/fsp2_0/include/fsp/debug.h index 43fad68d00..3708c679eb 100644 --- a/src/drivers/intel/fsp2_0/include/fsp/debug.h +++ b/src/drivers/intel/fsp2_0/include/fsp/debug.h @@ -30,6 +30,7 @@ void fspm_display_upd_values(const struct FSPM_UPD *old, const struct FSPM_UPD *new); void fsp_display_hobs(void); void fsp_verify_memory_init_hobs(void); +void fsp_print_header_info(const struct fsp_header *hdr); /* Callbacks for displaying UPD parameters - place in a separate file * that is conditionally build with CONFIG_DISPLAY_UPD_DATA. diff --git a/src/drivers/intel/fsp2_0/include/fsp/info_header.h b/src/drivers/intel/fsp2_0/include/fsp/info_header.h index f5db37d1c8..81639fa7d8 100644 --- a/src/drivers/intel/fsp2_0/include/fsp/info_header.h +++ b/src/drivers/intel/fsp2_0/include/fsp/info_header.h @@ -42,7 +42,6 @@ struct fsp_header { }; enum cb_err fsp_identify(struct fsp_header *hdr, const void *fsp_blob); -void fsp_print_header_info(const struct fsp_header *hdr); void fsp_print_upd_info(const struct fsp_header *hdr, void *cfg_blob); #if ENV_RAMSTAGE diff --git a/src/drivers/intel/fsp2_0/util.c b/src/drivers/intel/fsp2_0/util.c index 108457d7dd..bab060159d 100644 --- a/src/drivers/intel/fsp2_0/util.c +++ b/src/drivers/intel/fsp2_0/util.c @@ -59,49 +59,6 @@ enum cb_err fsp_identify(struct fsp_header *hdr, const void *fsp_blob) return CB_SUCCESS; } -void fsp_print_header_info(const struct fsp_header *hdr) -{ - union { - uint32_t val; - struct { - uint8_t bld_num; - uint8_t revision; - uint8_t minor; - uint8_t major; - } rev; - } revision; - - revision.val = hdr->fsp_revision; - - printk(BIOS_DEBUG, "Spec version: v%u.%u\n", (hdr->spec_version >> 4 ), - hdr->spec_version & 0xf); - printk(BIOS_DEBUG, "Revision: %u.%u.%u, Build Number %u\n", - revision.rev.major, - revision.rev.minor, - revision.rev.revision, - revision.rev.bld_num); - printk(BIOS_DEBUG, "Type: %s/%s\n", - (hdr->component_attribute & 1 ) ? "release" : "debug", - (hdr->component_attribute & 2 ) ? "test" : "official"); - printk(BIOS_DEBUG, "image ID: %s, base 0x%lx + 0x%zx\n", - hdr->image_id, hdr->image_base, hdr->image_size); - printk(BIOS_DEBUG, "\tConfig region 0x%zx + 0x%zx\n", - hdr->cfg_region_offset, hdr->cfg_region_size); - - if ((hdr->component_attribute >> 12) == FSP_HDR_ATTRIB_FSPM) { - printk(BIOS_DEBUG, "\tMemory init offset 0x%zx\n", - hdr->memory_init_entry_offset); - } - - if ((hdr->component_attribute >> 12) == FSP_HDR_ATTRIB_FSPS) { - printk(BIOS_DEBUG, "\tSilicon init offset 0x%zx\n", - hdr->silicon_init_entry_offset); - printk(BIOS_DEBUG, "\tNotify phase offset 0x%zx\n", - hdr->notify_phase_entry_offset); - } - -} - enum cb_err fsp_validate_component(struct fsp_header *hdr, const struct region_device *rdev) { @@ -123,7 +80,8 @@ enum cb_err fsp_validate_component(struct fsp_header *hdr, rdev_munmap(rdev, membase); - fsp_print_header_info(hdr); + if (IS_ENABLED(CONFIG_DISPLAY_FSP_HEADER)) + fsp_print_header_info(hdr); /* Check if size specified in the header matches the cbfs file size */ if (region_device_sz(rdev) < hdr->image_size) { -- cgit v1.2.3