From 6aea6f7a6b524d86be4fbdaf434aeda6d9f721a9 Mon Sep 17 00:00:00 2001 From: Kyösti Mälkki Date: Sun, 30 Jul 2017 09:01:24 +0300 Subject: usbdebug: Force EHCI to D0 state MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit When resuming from ACPI S3 suspend, EHCI controller may be in D3 power-management state. Bring it to D0 early so it is functional for console. NOTE: D3hot->D0 transition was observed to reset previous programming of PCI_COMMAND register. Change-Id: Id177ce61926beb057fe67ba42a306d8e565d2657 Signed-off-by: Kyösti Mälkki Reviewed-on: https://review.coreboot.org/20827 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel Reviewed-by: Patrick Rudolph --- src/drivers/usb/pci_ehci.c | 9 +++++++++ 1 file changed, 9 insertions(+) (limited to 'src/drivers/usb/pci_ehci.c') diff --git a/src/drivers/usb/pci_ehci.c b/src/drivers/usb/pci_ehci.c index 9099976ad5..73c709cdd8 100644 --- a/src/drivers/usb/pci_ehci.c +++ b/src/drivers/usb/pci_ehci.c @@ -44,6 +44,15 @@ int ehci_debug_hw_enable(unsigned int *base, unsigned int *dbg_offset) if (class != PCI_EHCI_CLASSCODE) return -1; + u8 pm_cap = pci_find_capability(dev, PCI_CAP_ID_PM); + if (pm_cap) { + u16 pm_ctrl = pci_read_config16(dev, pm_cap + PCI_PM_CTRL); + /* Set to D0 and disable PM events. */ + pm_ctrl &= ~PCI_PM_CTRL_PME_ENABLE; + pm_ctrl &= ~PCI_PM_CTRL_STATE_MASK; + pci_write_config16(dev, pm_cap + PCI_PM_CTRL, pm_ctrl); + } + u8 pos = pci_find_capability(dev, PCI_CAP_ID_EHCI_DEBUG); if (!pos) return -1; -- cgit v1.2.3