From 7524400242be26610df143b5d1d781f875239c45 Mon Sep 17 00:00:00 2001 From: Philipp Hug Date: Sat, 7 Jul 2018 21:34:31 +0200 Subject: uart/sifive: make divisor configurable MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The SiFive UART on the HiFive Unleashed uses the tlclk as input clock which runs at coreclk / 2. The input frequency is configured in the board code depending on the current stage. (bootblock + romstage run at 33.33Mhz, ramstage at 1Ghz) Change-Id: Iaf66723dba3d308f809fde5b05dfc3e43f43bd42 Signed-off-by: Philipp Hug Reviewed-on: https://review.coreboot.org/27440 Tested-by: build bot (Jenkins) Reviewed-by: Jonathan Neuschäfer --- src/drivers/uart/sifive.c | 15 +++++++++++---- 1 file changed, 11 insertions(+), 4 deletions(-) (limited to 'src/drivers/uart') diff --git a/src/drivers/uart/sifive.c b/src/drivers/uart/sifive.c index dd47cafcf1..ce8ead0d05 100644 --- a/src/drivers/uart/sifive.c +++ b/src/drivers/uart/sifive.c @@ -46,11 +46,10 @@ struct sifive_uart_registers { #define IP_TXWM BIT(0) #define IP_RXWM BIT(1) -void uart_init(int idx) +static void sifive_uart_init(struct sifive_uart_registers *regs, int div) { - struct sifive_uart_registers *regs = uart_platform_baseptr(idx); - - /* TODO: Configure the divisor */ + /* Configure the divisor */ + write32(®s->div, div); /* Enable transmission, one stop bit, transmit watermark at 1 */ write32(®s->txctrl, TXCTRL_TXEN|TXCTRL_NSTOP(1)|TXCTRL_TXCNT(1)); @@ -59,6 +58,14 @@ void uart_init(int idx) write32(®s->rxctrl, RXCTRL_RXEN|RXCTRL_RXCNT(0)); } +void uart_init(int idx) +{ + unsigned int div; + div = uart_baudrate_divisor(get_uart_baudrate(), + uart_platform_refclk(), uart_input_clock_divider()); + sifive_uart_init(uart_platform_baseptr(idx), div); +} + static bool uart_can_tx(struct sifive_uart_registers *regs) { return !(read32(®s->txdata) & TXDATA_FULL); -- cgit v1.2.3