From 148762110c8a00c88b8e0326ec69dc7392bf3739 Mon Sep 17 00:00:00 2001 From: Lee Leahy Date: Wed, 4 May 2016 13:13:20 -0700 Subject: drivers/uart: Enable override for input clock divider Allow the platform to override the input clock divider by adding the uart_input_clock_divider routine. This routine combines the baud-rate oversample divider with any other input clock divider. The default routine returns 16 which is the standard baud-rate oversampling value. A platform may override this default "weak" routine by providing a new routine and selecting UART_OVERRIDE_INPUT_CLOCK_DIVIDER. This works around ROMCC not supporting weak routines. Testing on Galileo: * Edit the src/mainboard/intel/galileo/Makefile.inc file: * Add "select ADD_FSP_PDAT_FILE" * Add "select ADD_FSP_RAW_BIN" * Add "select ADD_RMU_FILE" * Place the FSP.bin file in the location specified by CONFIG_FSP_FILE * Place the pdat.bin files in the location specified by CONFIG_FSP_PDAT_FILE * Place the rmu.bin file in the location specified by CONFIG_RMU_FILE * Build EDK2 CorebootPayloadPkg/CorebootPayloadPkgIa32.dsc to generate UEFIPAYLOAD.fd * Testing is successful when CorebootPayloadPkg is able to properly initialize the serial port without using built-in values. Change-Id: Ieb6453b045d84702b8f730988d0fed9f253f63e2 Signed-off-by: Lee Leahy Reviewed-on: https://review.coreboot.org/14611 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth --- src/drivers/uart/util.c | 17 +++++++++++++++++ 1 file changed, 17 insertions(+) (limited to 'src/drivers/uart/util.c') diff --git a/src/drivers/uart/util.c b/src/drivers/uart/util.c index 4121f60852..5e8d223252 100644 --- a/src/drivers/uart/util.c +++ b/src/drivers/uart/util.c @@ -42,3 +42,20 @@ unsigned int uart_baudrate_divisor(unsigned int baudrate, { return (1 + (2 * refclk) / (baudrate * oversample)) / 2; } + +#if !IS_ENABLED(CONFIG_UART_OVERRIDE_INPUT_CLOCK_DIVIDER) +unsigned int uart_input_clock_divider(void) +{ + /* Specify the default oversample rate for the UART. + * + * UARTs oversample the receive data. The UART's input clock first + * enters the baud-rate divider to generate the oversample clock. Then + * the UART typically divides the result by 16. The asynchronous + * receive data is synchronized with the oversample clock and when a + * start bit is detected the UART delays half a bit time using the + * oversample clock. Samples are then taken to verify the start bit and + * if present, samples are taken for the rest of the frame. + */ + return 16; +} +#endif -- cgit v1.2.3