From 1a5f25ea7f12d76425c6b66b3ff5cca3bb496296 Mon Sep 17 00:00:00 2001 From: Furquan Shaikh Date: Wed, 3 Feb 2021 23:02:34 -0800 Subject: intel: Drop FSP_PEIM_TO_PEIM_INTERFACE This change drops the config FSP_PEIM_TO_PEIM_INTERFACE. FSP_PEIM_TO_PEIM_INTERFACE is used for: * Auto-selecting FSP_USES_MP_SERVICES_PPI * Including src/drivers/intel/fsp2_0/ppi/Kconfig * Adding ppi to subdirs-y * Setting USE_INTEL_FSP_TO_CALL_COREBOOT_PUBLISH_MP_PPI to y and is selected by SoCs that want to enable MP PPI services. Instead of using the indirect path of selecting MP PPI services, this change allows SoC to select FSP_USES_MP_SERVICES_PPI directly. The above uses are handled as follows: * Auto-selecting FSP_USES_MP_SERVICES_PPI --> This is handled by SoC selection of FSP_USES_MP_SERVICES_PPI. * Including src/drivers/intel/fsp2_0/ppi/Kconfig --> The guard isn't really required. The Kconfig options in this file don't present user prompts and don't really need to be guarded. * Adding ppi to subdirs-y --> Makefile under ppi/ already has conditional inclusion of files and does not require a top-level conditional. * Setting USE_INTEL_FSP_TO_CALL_COREBOOT_PUBLISH_MP_PPI to y --> This is set to y if FSP_USES_MP_SERVICES_PPI is selected by SoC. TEST=Verified that timeless build for brya, volteer, icelake_rvp, elkhartlake_crb and waddledee shows no change in generated coreboot.rom Change-Id: I0664f09d85f5be372d19925d47034c76aeeef2ae Signed-off-by: Furquan Shaikh Reviewed-on: https://review.coreboot.org/c/coreboot/+/50274 Reviewed-by: Aamir Bohra Reviewed-by: Tim Wawrzynczak Reviewed-by: Subrata Banik Tested-by: build bot (Jenkins) --- src/drivers/intel/fsp2_0/Kconfig | 12 ------------ src/drivers/intel/fsp2_0/Makefile.inc | 3 +-- 2 files changed, 1 insertion(+), 14 deletions(-) (limited to 'src/drivers/intel') diff --git a/src/drivers/intel/fsp2_0/Kconfig b/src/drivers/intel/fsp2_0/Kconfig index 3cff8fa111..d294786889 100644 --- a/src/drivers/intel/fsp2_0/Kconfig +++ b/src/drivers/intel/fsp2_0/Kconfig @@ -180,16 +180,6 @@ config FSP_PLATFORM_MEMORY_SETTINGS_VERSIONS This allows deployed systems to bump their version number with the same FSP which will trigger a retrain of the memory. -config FSP_PEIM_TO_PEIM_INTERFACE - bool - select FSP_USES_MP_SERVICES_PPI - help - This option allows SOC user to create specific PPI for Intel FSP - usage, coreboot will provide required PPI structure definitions - along with all APIs as per EFI specification. So far this feature - is limited till EFI_PEI_MP_SERVICE_PPI and this option might be - useful to add further PPI if required. - config HAVE_FSP_LOGO_SUPPORT bool default n @@ -279,8 +269,6 @@ config SOC_INTEL_COMMON_FSP_RESET will use the FSP EAS v2.0 section 12.2.2 (OEM Status Code) to indicate that a reset is required. -if FSP_PEIM_TO_PEIM_INTERFACE source "src/drivers/intel/fsp2_0/ppi/Kconfig" -endif endif diff --git a/src/drivers/intel/fsp2_0/Makefile.inc b/src/drivers/intel/fsp2_0/Makefile.inc index b518bec180..094308022a 100644 --- a/src/drivers/intel/fsp2_0/Makefile.inc +++ b/src/drivers/intel/fsp2_0/Makefile.inc @@ -95,7 +95,6 @@ ifneq ($(call strip_quotes,$(CONFIG_FSP_HEADER_PATH)),) CPPFLAGS_common+=-I$(CONFIG_FSP_HEADER_PATH) endif -# Include PPI directory of CONFIG_FSP_PEIM_TO_PEIM_INTERFACE is enable -subdirs-$(CONFIG_FSP_PEIM_TO_PEIM_INTERFACE) += ppi +subdirs-y += ppi endif -- cgit v1.2.3