From 0d34a50a360228138ade623e799b03eaba83b0a5 Mon Sep 17 00:00:00 2001 From: Martin Roth Date: Sat, 31 Dec 2022 18:27:22 -0700 Subject: src: Move POST_BOOTBLOCK_CAR to common postcodes and use it This moves the definition for POST_BOOTBLOCK_CAR from the intel-specific postcodes into the common postcode list, and uses it for the cache-as-RAM init as needed. Because POST_BOOTBLOCK_CAR was set to 0x20 in some spots and 0x21 in most of the others, the values were consolidated into 0x21. This will change the value on some platforms. Any conflicts should get sorted out later in the conversion process. Signed-off-by: Martin Roth Change-Id: I8527334e679a23006b77a5645f919aea76dd4926 Reviewed-on: https://review.coreboot.org/c/coreboot/+/71596 Tested-by: build bot (Jenkins) Reviewed-by: Elyes Haouas --- src/drivers/intel/fsp1_1/cache_as_ram.S | 4 +--- 1 file changed, 1 insertion(+), 3 deletions(-) (limited to 'src/drivers/intel') diff --git a/src/drivers/intel/fsp1_1/cache_as_ram.S b/src/drivers/intel/fsp1_1/cache_as_ram.S index 6a19b870f2..571feb4f92 100644 --- a/src/drivers/intel/fsp1_1/cache_as_ram.S +++ b/src/drivers/intel/fsp1_1/cache_as_ram.S @@ -34,7 +34,7 @@ bootblock_pre_c_entry: movd %eax, %mm1 cache_as_ram: - post_code(0x20) + post_code(POST_BOOTBLOCK_CAR) /* Cache the rom and update the microcode */ cache_rom: @@ -181,8 +181,6 @@ CAR_init_done: pushl %eax /* tsc[31:0] */ before_romstage: - post_code(0x2a) - /* Call bootblock_c_entry(uint64_t base_timestamp) */ call bootblock_c_entry -- cgit v1.2.3