From bac23033d3d2c3094d905a6adf9f6233f6278c14 Mon Sep 17 00:00:00 2001
From: Patrick Rudolph <siro@das-labor.org>
Date: Fri, 30 Jun 2017 15:18:23 +0200
Subject: drv/intel/gma/opregion: Add method to restore ASLS

Add a new method to restore ASLS on S3 resume.
Use new interface introduced in last commit.

Change-Id: I254683081cbaf3a5938794dcba140ac9ee07f48a
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-on: https://review.coreboot.org/20436
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
---
 src/drivers/intel/gma/opregion.c | 16 ++++++++++++++++
 1 file changed, 16 insertions(+)

(limited to 'src/drivers/intel/gma/opregion.c')

diff --git a/src/drivers/intel/gma/opregion.c b/src/drivers/intel/gma/opregion.c
index ab9093b82f..721a5d8239 100644
--- a/src/drivers/intel/gma/opregion.c
+++ b/src/drivers/intel/gma/opregion.c
@@ -18,6 +18,8 @@
 #include <device/pci.h>
 #include <device/pci_ids.h>
 #include <device/pci_ops.h>
+#include <console/console.h>
+#include <cbmem.h>
 #include "opregion.h"
 
 /* Write ASLS PCI register and prepare SWSCI register. */
@@ -46,3 +48,17 @@ void intel_gma_opregion_register(uintptr_t opregion)
 	reg16 |= SMISCISEL;
 	pci_write_config16(igd, SWSCI, reg16);
 }
+
+/* Restore ASLS register on S3 resume and prepare SWSCI. */
+void intel_gma_restore_opregion(void)
+{
+	if (acpi_is_wakeup_s3()) {
+		const void *const gnvs = cbmem_find(CBMEM_ID_ACPI_GNVS);
+		uintptr_t aslb;
+
+		if (gnvs && (aslb = gma_get_gnvs_aslb(gnvs)))
+			intel_gma_opregion_register(aslb);
+		else
+			printk(BIOS_ERR, "Error: GNVS or ASLB not set.\n");
+	}
+}
-- 
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